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參數(shù)資料
| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| 中文描述： | 奔騰過驅(qū)動處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動處理器） |
| 文件頁數(shù)： | 16/61頁 |
| 文件大?。?/td> | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
16
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
(Continued)
Symbol
Type
Name and Function
D/C#
O
The data/code output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.
D/P#
O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
D63-D0
I/O
These are the 64 data lines for the processor. Lines D7-D0 define the least
significant byte of the data bus; lines D63-D56 define the most significant byte of
the data bus. When the CPU is driving the data lines, they are driven during the
T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data
bus when BRDY# is returned.
DP7-DP0
I/O
These are the data parity pins for the processor. There is one for each byte of
the data bus. They are driven by Pentium OverDrive processor with MMX
technology with even parity information on writes in the same clock as write
data. Even parity information must be driven back to the Pentium OverDrive
processor with MMX technology on these pins in the same clock as the data to
ensure that the correct parity check status is indicated by the Pentium
OverDrive processor with MMX technology. DP7 applies to D63-D56, DP0
applies to D7-D0.
[DPEN#]
PICD0
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
EADS#
I
This signal indicates that a valid external address has been driven onto the
Pentium OverDrive processor with MMX technology address pins to be used for
an inquire cycle.
EWBE#
I
The external write buffer empty input, when inactive (high), indicates that a write
cycle is pending in the external system. When Pentium OverDrive processor
with MMX technology generates a write, and EWBE# is sampled inactive, the
Pentium OverDrive processor with MMX technology will hold off all subsequent
writes to all E- or M-state lines in the data cache until all write cycles have
completed, as indicated by EWBE# being active.
FERR#
O
The floating-point error pin is driven active when an unmasked floating-point
error occurs. FERR# is similar to the ERROR# pin on the Intel387 math
coprocessor. FERR# is included for compatibility with systems using DOS-type
floating-point error reporting.
FLUSH#
I
When asserted, the cache flush input forces the Pentium OverDrive processor
with MMX technology to writeback all modified lines in the data cache and
invalidate its internal caches. A Flush Acknowledge special cycle will be
generated by the Pentium OverDrive processor with MMX technology indicating
completion of the writeback and invalidation.
If FLUSH# is sampled low when RESET transitions from high to low, tristate test
mode is entered.
FRCMC#
I
The Pentium OverDrive processor with MMX technology does not support
functional redundancy checking.
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