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參數(shù)資料
| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術奔騰超速轉動處理器) |
| 中文描述： | 奔騰過驅動處理器的MMX技術的Pentium處理器為基礎的系統(tǒng)（帶MMX公司技術奔騰超速轉動處理器） |
| 文件頁數(shù)： | 17/61頁 |
| 文件大?。?/td> | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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E
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
17
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
(Continued)
Symbol
Type
Name and Function
HIT#
O
The hit indication is driven to reflect the outcome of an inquire cycle. If an inquire
cycle hits a valid line in either Pentium OverDrive processor with MMX
technology data or instruction cache, this pin is asserted two clocks after
EADS# is sampled asserted. If the inquire cycle misses the Pentium OverDrive
processor with MMX technology cache, this pin is negated two clocks after
EADS#. This pin changes its value only as a result of an inquire cycle and
retains its value between the cycles.
HITM#
O
The hit to a modified line output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line
in the data cache. It is used to inhibit another bus master from accessing the
data until the line is completely written back.
HLDA
O
The bus hold acknowledge pin goes active in response to a hold request driven
to the processor on the HOLD pin. It indicates that Pentium OverDrive
processor with MMX technology has floated most of the output pins and
relinquished the bus to another local bus master. When leaving bus hold, HLDA
will be driven inactive and Pentium OverDrive processor with MMX technology
will resume driving the bus. If the Pentium OverDrive processor with MMX
technology has a bus cycle pending, it will be driven in the same clock that
HLDA is de-asserted.
HOLD
I
In response to the bus hold request, Pentium OverDrive processor with MMX
technology will float most of its output and input/output pins and assert HLDA
after completing all outstanding bus cycles. The Pentium OverDrive processor
with MMX technology will maintain its bus in this state until HOLD is de-
asserted. HOLD is not recognized during LOCK cycles. The Pentium OverDrive
processor with MMX technology will recognize HOLD during reset.
IERR#
O
The internal error pin is used to indicate internal parity errors. If a parity error
occurs on a read from an internal array, the Pentium OverDrive processor with
MMX technology will assert the IERR# pin for one clock and then shutdown.
IGNNE#
I
This is the ignore numeric error input. This pin has no effect when the NE bit in
CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the
Pentium OverDrive processor with MMX technology will ignore any pending
unmasked numeric exception and continue executing floating-point instructions
for the entire duration that this pin is asserted. When the CR0.NE bit is 0,
IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES
= 1), and the floating-point instruction is one of FINIT, FCLEX, FSTENV,
FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium OverDrive
processor with MMX technology will execute the instruction in spite of the
pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a
pending unmasked numeric exception exists (SW.ES = 1), and the floating-point
instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW,
FSTCW, FENI, FDISI, or FSETPM, the Pentium OverDrive processor with MMX
technology will stop execution and wait for an external interrupt.
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