參數(shù)資料
型號(hào)： Pentium OverDrive Processor
廠商： Intel Corp.
英文描述： Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器)
中文描述： 奔騰過(guò)驅(qū)動(dòng)處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器）
文件頁(yè)數(shù)： 18/61頁(yè)
文件大?。?/td> 481K
代理商： PENTIUM OVERDRIVE PROCESSOR
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
18
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
(Continued)
Symbol
Type
Name and Function
INIT
I
The Pentium OverDrive processor with MMX technology
initialization
input pin
forces the Pentium OverDrive processor with MMX technology to begin
execution in a known state. The processor state after INIT is the same as the
state after RESET except that the internal caches, write buffers, and floating-
point registers retain the values they had prior to INIT. INIT may NOT be used in
lieu of RESET after power up.
If INIT is sampled high when RESET transitions from high to low, the Pentium
OverDrive processor with MMX technology will perform built-in self test prior to
the start of program execution.
INTR/LINT0
I
An active maskable interrupt input indicates that an external interrupt has been
generated. If the IF bit in the EFLAGS register is set, the Pentium OverDrive
processor with MMX technology will generate two locked interrupt acknowledge
bus cycles and vector to an interrupt handler after the current instruction
execution is completed. INTR must remain active until the first interrupt
acknowledge cycle is generated to assure that the interrupt is recognized.
INV
I
The invalidation input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in
the clock EADS# is sampled active.
KEN#
I
The cache enable pin is used to determine whether the current cycle is
cacheable or not and is consequently used to determine cycle length. When the
Pentium OverDrive processor with MMX technology generates a cycle that can
be cached (CACHE# asserted) and KEN# is active, the cycle will be
transformed into a burst line fill cycle.
LOCK#
O
The bus lock pin indicates that the current bus cycle is locked. Pentium
OverDrive processor with MMX technology will not allow a bus hold when
LOCK# is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active
in the first clock of the first locked bus cycle and goes inactive after the BRDY#
is returned for the last locked bus cycle. LOCK# is guaranteed to be deasserted
for at least one clock between back to back locked cycles.
M/IO#
O
The memory/input-output is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO#
distinguishes between memory and I/O cycles.
NA#
I
An active next address input indicates that the external memory system is ready
to accept a new bus cycle although all data transfers for the current cycle have
not yet completed. The Pentium OverDrive processor with MMX technology will
issue ADS# for a pending cycle two clocks after NA# is asserted. The Pentium
OverDrive processor with MMX technology supports up to 2 outstanding bus
cycles.
NMI/LINT1
I
The non-maskable interrupt request signal indicates that an external non-
maskable interrupt has been generated.
PBGNT#
I/O
The Pentium OverDrive processor with MMX technology does not support dual
processing.
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