E
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
3
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
CONTENTS
PAGE
PAGE
1.0. INTRODUCTION ...............................................5
1.1. Product Overview...........................................5
1.2. Product Description........................................8
1.3. Purpose of this Document..............................8
1.4. Compatibility Note ..........................................8
2.0. PINOUT AND PIN DESCRIPTION....................8
2.1. Pinout..............................................................8
2.2. Pin Cross Reference....................................11
2.3. Quick Pin Reference ....................................14
2.4. Pin Descriptions ...........................................22
2.4.1. INPUT PINS..........................................22
2.4.2. OUTPUT PINS......................................24
2.4.3. INPUT/OUTPUT PINS..........................25
2.4.4. PIN GROUPING ACCORDING TO
FUNCTION ...........................................26
3.0. COMPONENT OPERATION...........................27
3.1. Core to Bus Ratio for Higher Speed.............27
3.2. Hardware Interface Differences ...................27
3.2.1. CPUTYP SIGNAL .................................27
3.3. Processor Initialization .................................27
3.3.1. POWER UP SPECIFICATION..............27
3.3.2. TEST AND CONFIGURATION
FEATURES (BIST, FRC, TRISTATE
TEST MODE)........................................28
3.3.3. INITIALIZATION WITH RESET, INIT
AND BIST .............................................28
3.4. Instruction Differences..................................28
3.4.1. MMX TECHNOLOGY EXTENSIONS
TO THE INTEL ARCHITECTURE........28
3.4.2. RDPMC (READ PERFORMANCE
MONITORING COUNTER)..................28
3.5. CPUID ..........................................................28
3.6. On-Package Fan/Heatsink...........................30
3.7. On-Package Voltage Regulator....................30
3.8. Cache Support..............................................30
3.9. Code Prefetch Queue and Branch Target
Buffers..........................................................30
3.10. I/O Buffers ..................................................30
3.11. Test Register Access.................................30
4.0. BIOS AND SOFTWARE..................................31
5.0. ELECTRICAL SPECIFICATIONS...................31
5.1. Power and Ground .......................................31
5.2. Decoupling Recommendations.....................31
5.3. Other Connection Recommendations..........31
5.4. Absolute Maximum Ratings..........................31
5.5. D.C. Specifications.......................................33
5.6. A.C. Specifications .......................................34
5.6.1. A. C. TABLES FOR A 50-MHZ BUS.....34
5.6.2. A. C. TABLES FOR A 60-MHZ BUS.....38
5.6.3. A. C. TABLES FOR A 66-MHZ BUS.....42
5.6.4. TIMING AND WAVEFORMS ................46
6.0. MECHANICAL SPECIFICATIONS .................50
6.1. Package Dimensions....................................50
6.2. Spatial Requirements ...................................52
6.3. Socket...........................................................53
6.3.1. SOCKET COMPATIBILITY...................53
6.3.2. SOCKET 5 PINOUT..............................53
6.3.3. SOCKET 7 PINOUT..............................54
7.0. THERMAL SPECIFICATIONS........................57
8.0. TESTABILITY..................................................57
8.1. Introduction...................................................57
8.2. Built in Self Test (BIST)................................57
8.3. Tri-State Test Mode......................................57