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| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| 中文描述： | 奔騰過驅(qū)動處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動處理器） |
| 文件頁數(shù)： | 41/61頁 |
| 文件大小： | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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E
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
41
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 16. 60-MHz Bus A.C. Specifications
(Continued)
3.135 < V
CC
< 3.6V, T
A
= 10 to 45
°
C, C
L
= 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
t
57
All Non-Test Inputs Setup Time
5.0
nS
12
(3), (7), (10)
t
58
All Non-Test Inputs Hold Time
13.0
nS
12
(3), (7), (10)
NOTES:
Notes 2, 6, and 13 are general and apply to all standard TTL signals used with the Pentium
OverDrive processor with
MMX technology.
1.
Not 100% tested. Guaranteed by design/characterization.
2.
TTL input test waveforms are assumed to be 0 to 3 Volt transitions with 1Volt/nS rise and fall times.
3.
Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to boundary scan operations.
4.
APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch free outputs. Glitch free signals monotonically transition
without false transitions (i.e., glitches).
5.
0.8 V/ns <= CLK input rise/fall time <= 8 V/ns.
6.
0.3 V/ns <= Input rise/fall time <= 5 V/ns.
7.
Referenced to TCK rising edge.
8.
Referenced to TCK falling edge.
9.
1ns can be added to the max TCK rise and fall times for every 10 MHz of frequency below 33 MHz.
10. During probe mode operation, do not use the boundary scan timings (t
55-58
).
11. Setup time is required to guarantee recognition on a specific clock. This is not applicable to the Pentium OverDrive
processor with MMX technology.
12. Hold time is required to guarantee recognition on a specific clock.
13. All TTL timings are referenced from 1.5 V.
14. To guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of 2
clocks before being returned active and must meet the minimum pulse width.
15. This input may be driven asynchronously. However, when operating the Pentium
OverDrive
processor with MMX
technology, FLUSH# and RESET must be asserted synchronously.
16. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be deasserted (inactive) for a minimum
of 2 clocks before being returned active.
17. The D/C#, M/IO#, W/R#, CACHE#, and A5-A31 signals are sampled only on the CLK that ADS# is active.
18. BF, BF1, and CPUTYP should be strapped to V
CC
or V
SS
.
19. These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the
amplitude of the input jitter and the internal and external clocks, the jitter frequency specturm should not have any power
spectrum peaking between 500KHz and 1/3 of the CLK operating frequency. The amount of jitter present must be
accounted for as a component of CLK skew between devices.
20. BRDYC# and BUSCHK# are used as Reset configuration signals to select buffer size.
21. The value of this signal may have been changed, check the latest Pentium Processor Data Book for the updated values.
** Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling to account for signal flight
time delays.
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