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參數(shù)資料
| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| 中文描述： | 奔騰過驅(qū)動處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動處理器） |
| 文件頁數(shù)： | 15/61頁 |
| 文件大小： | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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E
Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
15
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
(Continued)
Symbol
Type
Name and Function
BOFF#
I
The backoff input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the Pentium OverDrive processor with MMX
technology will float all pins normally floated during bus hold in the next clock.
The processor remains in bus hold until BOFF# is negated, at which time
Pentium OverDrive processor with MMX technology restarts the aborted bus
cycle(s) in their entirety.
BP[3:2]
PM/BP[1:0]
O
The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0.
These pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the performance monitoring pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if
the pins are configured as breakpoint or performance monitoring pins. The pins
come out of RESET configured for performance monitoring.
BRDY#
I
The burst ready input indicates that the external system has presented valid
data on the data pins in response to a read or that the external system has
accepted the Pentium OverDrive processor with MMX technology data in
response to a write request. This signal is sampled in the T2, T12 and T2P bus
states.
BRDYC#
I
This signal has the same functionality as BRDY#.
BREQ
O
The bus request output indicates to the external system that Pentium OverDrive
processor with MMX technology has internally generated a bus request. This
signal is always driven whether or not the Pentium OverDrive processor with
MMX technology is driving its bus.
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of
a bus cycle. If this pin is sampled active, Pentium OverDrive processor with
MMX technology will latch the address and control signals in the machine check
registers. If, in addition, the MCE bit in CR4 is set, the Pentium OverDrive
processor with MMX technology will vector to the machine check exception.
CACHE#
O
For Pentium OverDrive processor with MMX technology-initiated cycles the
cache pin indicates internal cacheability of the cycle (if a read), and indicates a
burst writeback cycle (if a write). If this pin is driven inactive during a read cycle,
Pentium OverDrive processor with MMX technology will not cache the returned
data, regardless of the state of the KEN# pin. This pin is also used to determine
the cycle length (number of transfers in the cycle).
CLK
I
The clock input provides the fundamental timing for Pentium OverDrive
processor with MMX technology. The clock frequency is the operating
frequency of the Pentium OverDrive processor with MMX technology external
bus and requires TTL levels. All external timing parameters except TDI, TDO,
TMS, TRST#, and PICD0-1 are specified with respect to the rising edge of CLK.
CPUTYP
I
CPUTYP is internally tied to ground and is a Internal No-Connect (INC) to the
package pin on the Pentium OverDrive processor with MMX technology.
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