參數(shù)資料
型號(hào)： pentium III processor
廠商： Intel Corp.
英文描述： 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 33/67頁(yè)
文件大?。?/td> 834K
代理商： PENTIUM III PROCESSOR
Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
243356-005
Datasheet
27
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
4.5.1.5
HALT/Grant Snoop State
The processor will respond to snoop transactions on the PSB while in the Auto Halt, Stop Grant, or
Quick Start state. When a snoop transaction is presented on the system bus, the processor will enter
the HALT/Grant Snoop state. The processor will remain in this state until the snoop has been
serviced and the PSB is quiet. After the snoop has been serviced, the processor will return to its
previous state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input
signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop state (except for
those signal transitions that are required to perform the snoop).
4.5.1.6
Sleep State
Intel mobile modules do not support the Sleep state.
In desktop systems, the Sleep state is a very low-power state in which the processor maintains its
context and the phase locked loop (PLL) maintains phase lock. The Sleep state can only be entered
from the Stop Grant state. After entering the Stop Grant state the SLP# signal can be asserted,
causing the processor to enter the Sleep state. The SLP# signal is not recognized in the Normal
state or the Auto Halt state.
The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven
active while the processor is in the Sleep state, then SLP# and STPCLK# must immediately be
driven inactive to ensure that the processor correctly initializes itself.
Input signals (other than RESET#) may not change while the processor is in or transitioning into or
out of the Sleep state. Input signal changes at these times will cause unpredictable behavior. Thus,
the processor is incapable of snooping or latching any events in the Sleep state.
While in the Sleep state the processor can enter its lowest power state, the Deep Sleep state.
Removing the processor's input clock puts the processor in the Deep Sleep state. PICCLK may be
removed in the Sleep state.
4.5.1.7
Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. The processor enters the Deep Sleep state by stopping the BCLK input while the processor
is in the Sleep state or the Quick Start state. For proper operation, the BCLK input should be
stopped in the low state.
The processor will return to the Sleep state or the Quick Start state from the Deep Sleep state when
the BCLK input is restarted. Due to the PLL lock latency, there is a 30.0-
μ
S delay after the clocks
have started before this state transition happens. PICCLK may be removed in the Deep Sleep state.
PICCLK should be designed to turn on when BCLK turns on while transitioning out of the Deep
Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that
RESET# assertion will result in unpredictable behavior.
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