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參數(shù)資料
| 型號： | pentium III processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| 中文描述： | 32位處理器的移動模塊（32位帶移動模塊處理器） |
| 文件頁數(shù)： | 20/67頁 |
| 文件大小： | 834K |
| 代理商： | PENTIUM III PROCESSOR |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
14
Datasheet
243356-005
3.1.8
Clock Signals
Table 8
provides descriptions of the clock signals.
Table 8. Clock Signal Descriptions
Name
Type
Voltage
Description
PCLK
I
PCI
V_3
PCI Clock In:
PCLK, an input to the mobile module, is one of the
system’s PCI clocks.
This clock is used by all of the 82443BX Host
Bridge logic in the PCI clock domain.
This clock is stopped when the
PIIX4E/M PCI_STP# signal is asserted "and/or" during all suspend
states.
HCLK0
I
CMOS
V_CLK
Host Clock In:
This clock is an input to the mobile module from the
CK100-M/CK100-SM clock source. The processor and the 82443BX
Host Bridge system controller use HCLK0. This clock is stopped when
the PIIX4E/M CPU_STP# signal is asserted "and/or" during all
suspend states.
Note
: The signal names HCLK0 and BCLK are used interchangeably.
HCLK1
I
CMOS
V_CLK
Host Clock In:
This clock is an input to the mobile module from the
CK100-M/CK100-SM clock source.
HCLK1 is not implemented on the mobile module.
DCLK0
O
CMOS
V_3
SDRAM Clock Out:
A 66-MHz SDRAM clock reference generated
internally by the 82443BX Host Bridge system controller onboard PLL.
It feeds an external buffer that produces multiple copies for the SO-
DIMMs.
DCLKRD
I
CMOS
V_3
SDRAM Read Clock:
A feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge System Controller uses this clock
when reading data from the SDRAM array.
DCLKRD is not implemented on the mobile module.
DCLKWR
I
CMOS
V_3
SDRAM Write Clock:
A feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge system controller uses this clock
when writing data to the SDRAM array.
GCLKIN
I
CMOS
V_3
AGP Clock In:
The GCLKIN input is a feedback reference from the
GCLKO signal.
GCLKO
O
CMOS
V_3
AGP Clock Out:
This signal is generated by the 82443BX Host
Bridge system controller onboard PLL from the HCLK0 host clock
reference. The frequency of GCLKO is 66 MHz. The GCLKO output is
used to feed both the PLL reference input pins on the 82443BX Host
Bridge system controller and the AGP device. The board layout must
maintain complete symmetry on loading and trace geometry to
minimize AGP clock skew.
FQS
O
CMOS
V_3S
Frequency Select:
This output indicates the desired host clock
frequency for the mobile module.
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