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參數(shù)資料
| 型號： | pentium III processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| 中文描述： | 32位處理器的移動模塊（32位帶移動模塊處理器） |
| 文件頁數(shù)： | 21/67頁 |
| 文件大?。?/td> | 834K |
| 代理商： | PENTIUM III PROCESSOR |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
243356-005
Datasheet
15
3.1.9
Voltage Signals
Table 9
provides descriptions of the voltage signals.
Table 9. Voltage Descriptions
Name
Type
Number
of pins
Description
V_DC
I
20
DC Input:
7.5V ~ 21.0V
V_3S
I
9
SUSB# controlled 3.3V:
A
power managed 3.3-V supply, and an
output of the voltage regulator on the system electronics. This rail
is off during STR, STD, and Soff.
V_5
I
3
SUSC# controlled 5.0V:
A
power managed 5.0-V supply.
An
output of the voltage regulator on the system electronics. This rail
is off during STD and Soff.
V_3
I
16
SUSC# controlled 3.3V:
A power managed 3.3-V supply.
An
output of the voltage regulator on the system electronics. This rail
is off during STD and Soff.
VCCAGP
I
4
AGP I/O Voltage
: This voltage rail is not implemented on the
mobile module and is defined for upgrade purposes only. Intel
recommends that this voltage rail be connected to V_3 on the
system electronics.
V_CPUPU
O
1
Processor I/O Ring:
The mobile module drives
V_CPUPU to
power the processor interface signals, such as the PIIX4E/M open-
drain pullups for the processor/PIIX4E/M sideband signals.
V_CPUPU is tied to 3.3V for the mobile module.
V_CLK
O
1
Processor Clock Rail:
The mobile module drives
V_CLK
to power
the CK100-M VDDCPU rail.
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