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參數(shù)資料
| 型號(hào)： | pentium III processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| 中文描述： | 32位處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器） |
| 文件頁(yè)數(shù)： | 17/67頁(yè) |
| 文件大?。?/td> | 834K |
| 代理商： | PENTIUM III PROCESSOR |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
243356-005
Datasheet
11
3.1.5
Intel SpeedStep Technology Signals
Table 5
provides the Intel speedstep technology signal descriptions.
SERR#
I/O
PCI
V_3
System Error:
The 82443BX asserts this signal to indicate an error
condition. For further information, refer to the
Intel
440BX AGPSet:
82443BX Host Bridge/Controller Datasheet (Order Number: 290633-
001)
.
CLKRUN#
I/O D
PCI
V_3
Clock Run:
An open-drain output and input.
The 82443BX Host
Bridge requests the central resource, PIIX4E/M, to start or maintain
the PCI clock by asserting CLKRUN#.
The 82443BX Host Bridge tri-
states CLKRUN# upon deassertion of reset (since CLK is running
upon deassertion of reset).
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the
82443BX Host Bridge.
The PCI signals also tri-state, compliant with
PCI Revision 2.1 Specifications
.
Table 4. PCI Signal Descriptions
Name
Type
Voltage
Description
Table 5. Intel SpeedStep Technology Signal Description
Name
Type
Voltage
Description
G_LOHI#
I
CMOS
V_3S
SpeedStep State Transition
: Generated by the system electronics,
this signal defines a SpeedStep state change to the SpeedStep state
machine. This signal must be high on the rising edge of VR_ON.
G_CPU_STP#
I
CMOS
V_3S
SpeedStep CPU_STP#
: The CPU_STP# signal must be gated on the
system electronics by VRCHGNG# and then routed to G_CPU_STP#
on the connector and to the clock generator.
VRCHGNG#
O D
CMOS
V_3S
Voltage Changing
: A SpeedStep state machine signal that indicates
that the actual state change is in progress – the VR setpoint has
changed and the VR is settling. When this signal deasserts, the new
SpeedStep state will settle on the processor. The system electronics
will use this signal to generate an SCI to force a transition out of deep
sleep. Also used to gate CPU_STP# on the system electronics.
G_SUS_STAT1#
O
CMOS
V_3
G_SUS_STAT1#:
The system electronics uses this signal to gate
SUS_STAT1# from the PIIX4E/M.
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