- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367854 > PDI1394L21 (NXP Semiconductors N.V.) Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) PDF資料下載
參數(shù)資料
| 型號： | PDI1394L21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) |
| 中文描述： | 全雙工鏈路層Ccontroller影音（全雙工視聽鏈接層控制器） |
| 文件頁數(shù)： | 5/54頁 |
| 文件大?。?/td> | 242K |
| 代理商： | PDI1394L21 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
5
8.0
APPLICATION DIAGRAM
MPEG OR DVC
DECODER
PDI1394L21
AV LINK
AV
INTERFACE
PDI1394Pxx
PHY
PHY–LINK
INTERFACE
HOST CONTROLLER
DATA 8/
ADDRESS 9/
INTERRUPT & CONTROL
1394 CABLE
INTERFACE
MPEG OR DVC
DECODER
AV
INTERFACE
SV00880
9.0
PIN DESCRIPTION
9.1
Host Interface
PIN No.
1, 2, 3, 4, 7, 8,
9, 10
5, 12, 23, 31,
38, 44, 50, 63,
73, 79, 87, 93
6, 13, 24, 32,
39, 45, 49, 64,
72, 78, 88, 94
14, 15, 16, 17,
18, 19, 20, 21,
22
PIN SYMBOL
I/O
NAME AND FUNCTION
HIF D[7:0]
I/O
Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
GND
Ground reference
V
DD
3.3V
±
0.3V power supply
HIF A[8:0]
I
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules.
25
HIF CS_N
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control and
status registers.
Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L21
internal registers is requested. (NOTE: HIF WR_N and HIF RD_N : if these are both LOW in
conjunction with HIF CS_N, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WR_N and tie HIF RD_N LOW.)
Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L21
internal registers is requested.
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L21. Read the General
Interrupt Register for more information. This pin is open drain and requires a 1K pull-up resistor.
Reset (active LOW). The asynchronous master reset to the PDI1394L21.
26
HIF WR_N
I
27
HIF RD_N
I
28
HIF INT_N
O
29
RESET_N
I
相關PDF資料 |
PDF描述 |
|---|---|
| PDI1394L41 | Content Protection AV Link Layer(內(nèi)容可保護的AV鏈接層控制器) |
| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P22 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P24 | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| PDI40C1D00 | |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。