Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
43
13.3.7
Asynchronous Receive Request (RREQ) – Base Address: 0x098
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
SV00297
3130
Reset Value 0x00000000
Bit 31..0:
R
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
RREQ:Quadlet of packet from receiver request queue (transfer register).
13.3.8
Asynchronous Receive Response (RRSP) – Base Address: 0x09C
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
SV00298
3130
Reset Value 0x00000000
Bit 31..0:
R
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
RRSP:Quadlet of packet from receiver response queue (transfer register).
13.3.9
Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
SV01077
29 28
27 26 25 24 23
22 21 20 19 18
17 16
15 14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
T
R
R
R
R
R
R
R
S
R
T
R
T
T
T
T
T
31 30
Reset Value 0x00000C00
Bit 31..17:
Bit 16:
Bit 15:
Bit 14:
R/W
R/W
R/W
R/W
Unused bits read ‘0’
RRSPQFULL: Receiver response queue did become full. Write a “1” to this bit to reset the interrupt.
RREQQFULL: Receiver request queue did become full. Write a “1” to this bit to reset the interrupt.
SIDQAV: Current quadlet in RREQ is self ID data. This bit is set only after a bus reset, not after reception of PHY
packets other than self IDs. This interrupt automatically resets when the quadlet is read.
RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RRSPQQAV: Receiver response queue quadlet available (in RRSP). This interrupt automatically resets when the
quadlet is read.
RREQQQAV: Receiver request queue quadlet available (in RREQ). This interrupt automatically resets when the
quadlet is read.
TIMEOUT: Split transaction response timeout. Write a “1” to this bit to reset the interrupt.
RCVDRSP: Solicited response received (within timeout interval). Write a “1” to this bit to reset the interrupt.
TRSPQFULL: Transmitter response queue did become full. Write a “1” to this bit to reset the interrupt.
TREQQFULL: Transmitter request queue did become full. Write a “1” to this bit to reset the interrupt.
TRSPQWRERR: Transmitter response queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
Bit 13:
R/W
Bit 12:
R/W
Bit 11:
R/W
Bit 10:
R/W
Bit 9:
R/W
Bit 8:
R/W
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
R/W
R/W
R/W
R/W
R/W
R/W
R/W