參數(shù)資料
型號： PDI1394L21
廠商： NXP Semiconductors N.V.
英文描述： Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述： 全雙工鏈路層Ccontroller影音（全雙工視聽鏈接層控制器）
文件頁數(shù)： 24/54頁
文件大?。?/td> 242K
代理商： PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
24
12.5.3
The PDI1394L21 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the
device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INT_N. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt
is indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be
acknowledged. To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing
the interrupt status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
Interrupts
12.5.3.1
When responding to an interrupt event generated by the PDI1394L21, or operating in polled mode, the first register examined is the GLOBCSR
register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,
the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all
the enabled interrupt status bits in their section of the AV Link Layer Controller.
Determining and Clearing Interrupts
Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy
diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication
will automatically clear in the GLOBCSR.
All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
12.5.3.2
Interrupt Hierarchy
18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
I
SV01076
7 6 5 4 3 2 1 0
3 2 1 0
ITXINTACK (0x02C)
IRXINTACK (0x04C)
ASYINTACK (0x0A0)
LNKPHYINTACK (0x008)
GLOBCSR (0x018)
HIF INT_N
P
C
F
P
P
A
S
H
A
C
T
C
C
C
C
C
I
T
T
D
I
I
D
S
I
I
C
C
R
F
S
A
I
I
L
16 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
T
R
R
R
R
R
R
R
S
R
T
R
T
T
T
T
T
6 5 4 3 2 1 0
R
I
8
I
9
7
I
I
8
I
10
I
9
Figure 24. Interrupt Hierarchy
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L40 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller
PDI1394L40BE 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144
PDI1394L40BE,518 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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