參數(shù)資料
型號: PDI1394L21
廠商: NXP Semiconductors N.V.
英文描述: Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述: 全雙工鏈路層Ccontroller影音(全雙工視聽鏈接層控制器)
文件頁數(shù): 36/54頁
文件大?。?/td> 242K
代理商: PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
36
13.2.6
Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01016
TAG
CHANNEL
SPD
31 30
O
C
S
EMI
Reset Value 0x00000000
Bit 15..14:
Bit 13..8:
Bit 5..4:
R/W
R/W
R/W
Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data.
Channel: Isochronous channel number.
Speed: Cable transmission speed (S100, S200, S400).
00 =
100Mbs
01 =
200Mbs
10 =
400Mbs
11 =
reserved
Sync: Code to insert in SY field of isochronous bus packet header. Bit 1 is odd/even bit used for encryption key
(0 = even, 1 = odd). Bit value determined by state of transmit port AVxENKEY pin. Some data encryption schemes
require that an ODD/EVEN bit accompany each application packet sent for the purpose of changing “keys” after
short intervals of time (makes breaking an encryption code more difficult). The PDI1394L21 uses the sync field
ODD/EVEN bit for this purpose. Data is inputted to the transmitting AV port accompanied by the state of the
ODD/EVEN bit presented to the AVx ENKEY pin. The pin state at the rising edge of the AVCLK as the first byte of
the packet determines the ODD/EVEN “key” state for that packet. The ODD/EVEN key state may change as often as
required, provided that 2 key changes do not appear in the transmit FIFO simultaneously. If this rule is observed, the
proper “key” state will accompany the packet on to the 1394 bus and through the receiving node’s receive FIFO. As
the packet is being outputted at the receive node’s PDI1394L21, the accompanying ODD/EVEN key state will be
output. The key state remains for all bytes of the packet. Typical change rates for the ODD/EVEN key are between
1 change per second and a change every 30 seconds.
Bit 3..0
R
13.2.7
The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams
before transmission over the 1394 bus.
Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
I
I
I
I
SV00916
3130
I
I
I
Reset Value 0x00000003
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R
R
R
R
R
R
R
ITM100LFT: Memory has 100 quadlets of space remaining before becoming full.
ITM256LFT: Memory has 256 quadlets of space remaining before becoming full.
IITM512LFT: Memory is
1
/
2
full.
ITXMF: memory is completely full, no storage available.
ITXMAF: almost full, exactly one quadlet of storage available.
ITXM5AV: at least 5 more quadlets of storage available.
ITXME: memory bank is empty (zero quadlets stored).
相關(guān)PDF資料
PDF描述
PDI1394L41 Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器)
PDI1394P21 3-port Physical Layer Interface(三端口物理層接口)
PDI1394P22 3-port Physical Layer Interface(三端口物理層接口)
PDI1394P24 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
PDI40C1D00
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L40 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller
PDI1394L40BE 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144
PDI1394L40BE,518 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel