參數(shù)資料
型號(hào)： PDI1394L21
廠商： NXP Semiconductors N.V.
英文描述： Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述： 全雙工鏈路層Ccontroller影音（全雙工視聽(tīng)鏈接層控制器）
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 242K
代理商： PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
33
13.2
AV (Isochronous) Transmitter and Receiver Registers
13.2.1
Isochronous
Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020
This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters
(TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the
MAXBL parameter when in MPEG-2 packing mode.
NOTE: When reset of isochronous transmitter is necessary, first disable the transmitter (place bit 4, EN_ITX, LOW), wait for FIFO to empty, then
reset the transmitter (place RST_ITX, bit 0, HIGH). This procedure will ensure that data in the FIFO is transmitted before reset.
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
E
E
R
SV00886
PM
TRDEL
MAXBL
3130
T
S
E
m
Reset Value 0x00000001
Bit 29..28:
R/W
TXAP_CLK: Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an application
clock for the isochronous Transmitter (and output) by programming it to ‘01’, ‘10’, or ‘11’.
The programming values are:
00
Input
01
24.576MHz
10
12.288MHz
11
6.144MHz
Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as transmitter and enabled will output this
clock signal on its AVxCLK pin.
TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper 4 bits of
cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field.
MAXBL: The (maximum) number of data blocks to be put in a payload.
ENXTMSTP: Enable External time stamp control. Allows an external time stamp (generated by the application) to be
inserted in place of the link-generated time stamp. Defaults to link generated time stamp. The application must
present the first byte of a quadlet-wide time stamp accompanied by the AVSYNC pulse (and AVVALID) to the
AVPORT. The external time stamp quadlet is inputted first, followed by the application data packet. The transmitted
packet size is now one quadlet larger than the original isochronous data packet—Set up the isochronous
transmitter accordingly with SPH = 1.
CAUTION
: Unless valid IEC 61883 time stamp format (based on the link cycle
timer) is used, the receiving node link chip must be equipped with a time stamp check disabling function similar to
the DIS_TSC bit (register 0X040, Bit 7). Please see section 13.2.8 for details.
SYT_DELAY: Programmable delay of AV1FSYNC and AV2FSYNC. Each cycle is 1 bus cycle, 125 s.
Reset value is “00”, a 3 cycle delay.
01 =
2 cycles
00 =
3 cycles
10 =
4 cycles
11 =
Reserved
EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This
bit also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled
(0), the current packet will be transmitted and then the transmitter will shut down.
PM: packing mode:
00 =
variable sized bus packets, most generic mode.
01 =
fixed size bus packets.
10 =
MPEG–2 packing mode.
11 =
No data, just CIP headers are transmitted.
EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.
Reset Isochronous Transmitter (RST_ITX): causes transmitter to be reset when ‘1’. In order for synchronous reset of
ITX to work properly, an AVxCLK (from either the internal or external source) must be present and ensure that the
reset bit is kept (programmed) HIGH for at least the duration of one AVxCLK period. Failure to do so may cause
the application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes
will be flushed from the FIFO and transmission will cease immediately.
Bit 27..16:
R/W
Bit 15..8:
Bit 7:
R/W
R/W
Bit 6..5:
R/W
Bit 4:
R/W
Bit 3..2:
R/W
Bit 1:
Bit 0:
R/W
R/W
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