參數(shù)資料
型號(hào): PDI1394L21
廠商: NXP Semiconductors N.V.
英文描述: Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述: 全雙工鏈路層Ccontroller影音(全雙工視聽鏈接層控制器)
文件頁(yè)數(shù): 38/54頁(yè)
文件大?。?/td> 242K
代理商: PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
38
13.2.9
This quadlet represents the last received header value when AV receiver is operating.
Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
S
QPC
FN
DBS
SV00286
E
F
3130
SID
Reset Value 0x00000000
Bit 31..30:
Bit 29..24
Bit 23.16:
Bit 15..14:
R
R
R
R
E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet
SID: Source ID, contains the node address of the sender of the isochronous data.
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet.
QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the
specified size.
SPH: Indicates that a CYCTM based time stamp is inserted before each application packet (25 bits specified in the
IEC 61883 International Standard).
Bit 13..11:
R
Bit 10:
R
13.2.10
Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048
E
F
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
SYT
SV00287
31 30
FDF
Reset Value 0x0000FFFF
Bit 31..30:
Bit 29..24:
Bit 23..0:
R
R
R
E1: End of Header, F1: Format: Should be set to 10 for second AV header quadlet.
FMT: Value inserted in the Format field.
FDF/SYT: If ‘‘EN FS” in Register IRXPKCTL (0x040) is set to ‘1’, then lower 16-bits are interpreted as SYT.
13.2.11
Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
C
R
S
C
I
F
S
I
SV00881
3130
I
I
I
Reset Value 0x00000000
Bit 10:
Bit 9:
Bit 8:
Bit 7:
R/W
R/W
R/W
R/W
IR100LFT: Isochronous memory bank is 100 quadlets from full. (924 of 1024 quadlets in queue)
IR256LFT: Isochronous data memory bank is 256 quadlets from full. (768 of 1024 quadlets are in the queue)
IR512LFT: Isochronous data memory bank is 50% full. (512 of 1024 quadlets are in the queue)
IRXFULL: Isochronous data memory bank has become full. This is a fatal error, the recommended action is to reset
and re-initialize the receiver.
IRXEMPTY: Isochronous data memory bank has become empty.
FSYNC: Pulse at fsync output.
SEQERR: Sequence error of data blocks.
CRCERR: CRC error in bus packet.
CIPTAGFLT: Faulty CIP header tag (E,F bits). i.e.: The CIP header did not meet the standard and the whole packet
is ignored.
RCVBP: Bus packet processing complete.
SQOV: Status queue overflow. This is a fatal error, the recommended action is to reset and re-initialize the receiver.
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
R/W
R/W
R/W
R/W
R/W
Bit 1:
Bit 0:
R/W
R/W
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