參數(shù)資料
型號(hào)： PCA9665N
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Fm+ parallel bus to I2C-bus controller
中文描述： I2C BUS CONTROLLER, PDIP20
封裝： 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20
文件頁(yè)數(shù)： 9/91頁(yè)
文件大?。?/td> 372K
代理商： PCA9665N
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
9 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the
CPU can read or write up to 68 bytes at a time. See
Section 8.1 “Configuration modes”
for
more detail.
Remark:
The I2CDAT register will capture the serial address as data when addressed via
the serial bus.
Remark:
In Byte mode only, the data register will capture data from the serial bus during
38h (arbitration lost in slave address + R/W or data bytes causing this data in I2CDAT to
be changed), so the I2CDAT register will need to be reloaded when the bus becomes free.
In Buffered mode, the data is not written in the data register when arbitration is lost, which
keeps the buffer intact.
7.3.1.4
The Control register, I2CCON (A1 = 1, A0 = 1)
I2CCON is an 8-bit read/write register. Two bits are affected by the bus controller
hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared
when a STOP condition is present on the I
2
C-bus. A Write to the I2CCON register via the
parallel interface automatically clears the SI bit, which causes the Serial Interrupt line to
be de-asserted and the next clock pulse on the SCL line to be generated.
Remark:
Since none of the registers should be written to via the parallel interface once
the Serial Interrupt line has been de-asserted, all the other registers that need to be
modified should be written to before the content of the I2CCON register is modified.
Table 9.
I2CDAT - Data register (A1 = 0, A0 = 1) bit allocation
6
5
SD6
SD5
7
4
3
2
1
0
SD7
SD4
SD3
SD2
SD1
SD0
Table 10.
Bit
7:0
I2CDAT - Data register (A1 = 0, A0 = 1) bit description
Symbol
Description
SD[7:0]
Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to
a HIGH level on the I
2
C-bus. A logic 0 corresponds to a LOW level on the bus.
Table 11.
I2CCON - Control register (A1 = 1, A0 = 1) bit allocation
6
5
ENSIO
STA
STO
7
4
3
SI
2
-
1
-
0
AA
MODE
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