參數(shù)資料
型號: PCA9665N
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Fm+ parallel bus to I2C-bus controller
中文描述: I2C BUS CONTROLLER, PDIP20
封裝: 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20
文件頁數(shù): 10/91頁
文件大小: 372K
代理商: PCA9665N
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
10 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Table 12.
Bit
7
I2CCON - Control register (A1 = 1, A0 = 1) bit description
Symbol Description
AA
The Assert Acknowledge flag.
AA = 1: If the AA flag is set, an acknowledge (LOW level on SDA) will be returned
during the acknowledge clock pulse on the SCL line when:
‘Own slave address’ has been received (as defined in I2CADR register).
A data byte has been received while the bus controller is in the Master
Receiver mode.
A data byte has been received while the bus controller is in the addressed
Slave Receiver mode.
AA = 0: if the AA flag is reset, a not acknowledge (HIGH level on SDA) will be
returned during the acknowledge clock pulse on SCL when:
‘Own slave address’ has been received (as defined in I2CADR register).
A data byte has been received while the PCA9665 is in the Master Receiver
mode.
A data byte has been received while the PCA9665 is in the addressed Slave
Receiver mode.
When the bus controller is in the addressed Slave Transmitter mode, state C8h
will be entered after the last data byte is transmitted and an ACK is received from
the Master Receiver (see
Figure 10
and
Figure 14
). When SI is cleared, the
PCA9665 enters the not addressed Slave Receiver mode, and the SDA line
remains at a HIGH level. In state C8h, the AA flag can be set again for future
address recognition.
When the PCA9665 is in the not addressed slave mode, its own slave address is
ignored. Consequently, no acknowledge is returned, and a serial interrupt is not
requested. Thus, the bus controller can be temporarily released from the I
2
C-bus
while the bus status is monitored. While the bus controller is released from the
bus, START and STOP conditions are detected, and serial data is shifted in.
Address recognition can be resumed at any time by setting the AA flag.
ENSIO
The bus controller enable bit.
ENSIO = 0: When ENSIO is ‘0’, the SDA and SCL outputs are in a
high-impedance state. SDA and SCL input signals are ignored, the PCA9665 is in
the ‘not addressed’ slave state. Internal oscillator is off.
ENSIO = 1: When ENSIO is ‘1’, the PCA9665 is enabled.
After the ENSIO bit is set to ‘1’, it takes 550
μ
s enable time for the internal
oscillator to start up and the serial interface to initialize. The PCA9665 will enter
either the master or the slave mode after this time. ENSIO should not be used to
temporarily release the PCA9665 from the I
2
C-bus since, when ENSIO is reset,
the I
2
C-bus status is lost. The AA flag should be used instead (see description of
the AA flag above).
In the following text, it is assumed that ENSIO = ‘1’ for Normal mode operation.
For power-up behavior, please refer to
Section 8.10 “Power-on reset”
.
6
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