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參數(shù)資料
| 型號： | PCA9665N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Fm+ parallel bus to I2C-bus controller |
| 中文描述： | I2C BUS CONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20 |
| 文件頁數(shù)： | 72/91頁 |
| 文件大?。?/td> | 372K |
| 代理商： | PCA9665N |
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PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
72 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
[1]
Parameters are valid over specified temperature and voltage range.
[2]
All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of
5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in
Figure 38
and
Figure 40
.
[3]
Test conditions for outputs: C
L
= 50 pF; R
L
= 500
, except open-drain outputs.
Test conditions for open-drain outputs: C
L
= 50 pF; R
L
= 1 k
pull-up to V
DD
.
Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.
[4]
[5]
Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
[6]
Upon reset, the full delay will be the sum of t
rst
and the RC time constant of the SDA and SCL bus.
Table 50.
V
CC
= 2.5 V
±
0.2 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified. (See
Table 49 on page 71
for 3.3 V)
Symbol
Parameter
Conditions
Initialization timing
t
init(po)
power-on initialization time
Serial interface initialization timing
t
init(sintf)
serial interface initialization time
[4]
from ENSIO bit HIGH
RESET timing (see
Figure 36
)
t
w(rst)
reset pulse width
t
rst
reset time
t
rec(rst)
reset recovery time
INT timing (see
Figure 37
)
t
as(int)
interrupt assert time
t
das(int)
interrupt de-assert time
Bus timing (see
Figure 38
and
Figure 40
)
t
su(A)
address setup time
to RD, WR LOW
t
h(A)
address hold time
from RD, WR LOW
t
su(CE_N)
CE setup time
to RD, WR LOW
t
h(CE_N)
CE hold time
from RD, WR LOW
t
w(RDL)
RD LOW pulse width
t
w(WRL)
WR LOW pulse width
t
d(DV)
data valid delay time
after RD and CE LOW
t
d(QZ)
data output float delay time
after RD or CE HIGH
t
su(Q)
data output setup time
before WR or CE HIGH (write cycle)
t
h(Q)
data output hold time
after WR HIGH
t
w(RDH)
RD HIGH pulse width
t
w(WRH)
WR HIGH pulse width
Dynamic characteristics (2.5 volt)
[1][2][3]
Min
Typ
Max
Unit
-
-
550
μ
s
-
-
550
μ
s
10
-
-
-
-
-
-
ns
ns
ns
[5][6]
250
0
-
-
-
-
550
20
ns
ns
0
13
0
0
20
20
-
-
12
0
18
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
22
17
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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| PCA9665N,112 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665PW | 制造商:NXP Semiconductors 功能描述:IC CNTRLR PARALLEL I2C 20TS 制造商:UNBRANDED 功能描述:UNIVERSAL BUS FUNCTIONS FM+12C BUS *NIC* 制造商:NXP Semiconductors 功能描述:IC, CNTRLR PARALLEL, I2C, 20TSSOP 制造商:NXP Semiconductors 功能描述:IC, CNTRLR PARALLEL, I2C, 20TSSOP; Interface Type:I2C, Parallel, SMBus; Interface Applications:I2C Bus & SMBus Systems Applications; Supply Voltage Min:2.3V; Supply Voltage Max:3.6V; Digital IC Case Style:TSSOP; No. of Pins:20; ;RoHS Compliant: Yes |
| PCA9665PW,112 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
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