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參數資料
| 型號： | PCA9665N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Fm+ parallel bus to I2C-bus controller |
| 中文描述： | I2C BUS CONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20 |
| 文件頁數： | 5/91頁 |
| 文件大小： | 372K |
| 代理商： | PCA9665N |
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PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
5 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
6.2 Pin description
[1]
HVQFN package die supply ground is connected to both the V
SS
pin and the exposed center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Table 2.
Symbol
Pin description
Pin
DIP20,
SO20,
TSSOP20
1
2
3
4
5
6
7
8
9
Type
Description
HVQFN20
D0
D1
D2
D3
D4
D5
D6
D7
i.c.
18
19
20
1
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Data bus:
Bidirectional 3-state data bus used to
transfer commands, data and status between the bus
controller and the CPU. D0 is the least significant bit.
internally connected:
must be left floating (pulled
LOW internally)
Supply ground
Write strobe:
When LOW and CE is also LOW, the
content of the data bus is loaded into the addressed
register. Data are latched on the rising edge of either
WR or CE.
Read strobe:
When LOW and CE is also LOW,
causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on
the falling edge of RD.
Chip Enable:
Active LOW input signal. When LOW,
data transfers between the CPU and the bus
controller are enabled on D0 to D7 as controlled by
the WR, RD and A0 to A1 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
Data are written into the addressed register on rising
edge of either CE or WR.
Address inputs:
Selects the bus controller’s internal
registers and ports for read/write operations.
V
SS
WR
10
11
7
[1]
8
power
I
RD
12
9
I
CE
13
10
I
A0
A1
INT
14
15
16
11
12
13
I
I
O
Interrupt request:
Active LOW, open-drain, output.
This pin requires a pull-up device.
Reset:
Active LOW input. A LOW level clears internal
registers and resets the I
2
C-bus state machine.
I
2
C-bus serial clock input/output (open-drain).
This pin requires a pull-up device.
I
2
C-bus serial data input/output (open-drain). This pin
requires a pull-up device.
Power supply:
2.3 V to 3.6 V
RESET
17
14
I
SCL
18
15
I/O
SDA
19
16
I/O
V
DD
20
17
power
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相關代理商/技術參數 |
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|---|---|
| PCA9665N,112 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665PW | 制造商:NXP Semiconductors 功能描述:IC CNTRLR PARALLEL I2C 20TS 制造商:UNBRANDED 功能描述:UNIVERSAL BUS FUNCTIONS FM+12C BUS *NIC* 制造商:NXP Semiconductors 功能描述:IC, CNTRLR PARALLEL, I2C, 20TSSOP 制造商:NXP Semiconductors 功能描述:IC, CNTRLR PARALLEL, I2C, 20TSSOP; Interface Type:I2C, Parallel, SMBus; Interface Applications:I2C Bus & SMBus Systems Applications; Supply Voltage Min:2.3V; Supply Voltage Max:3.6V; Digital IC Case Style:TSSOP; No. of Pins:20; ;RoHS Compliant: Yes |
| PCA9665PW,112 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665PW,118 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665PW,118-CUT TAPE | 制造商:NXP 功能描述:PCA9635 Series 1 MHz Fm + Parallel Bus to I2C-Bus Controller - TSSOP-20 |
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