參數(shù)資料
型號： PCA9665N
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Fm+ parallel bus to I2C-bus controller
中文描述： I2C BUS CONTROLLER, PDIP20
封裝： 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20
文件頁數(shù)： 13/91頁
文件大?。?/td> 372K
代理商： PCA9665N
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
13 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
7.3.2.3
The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)
I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the
PCA9665 when used as a bus master. The actual frequency is determined by t
HIGH
(time
where SCL is HIGH), t
LOW
(time where SCL is LOW), t
r
(rise time), and t
f
(fall time) values.
t
HIGH
and t
LOW
are calculated based on the values that are programmed into I2CSCLH
and I2CSCLL registers and the internal oscillator frequency. t
r
and t
f
are
system/application dependent.
with T
osc
= internal oscillator period = 35 ns
±
5 ns
Remark:
The I2CMODE register needs to be programmed before programming the
I2CSCLL and I2CSCLH registers in order to know which I
2
C-bus mode is selected. See
Section 7.3.2.6 “The I
2
C-bus mode register, I2CMODE (indirect address 06h)”
for more
detail.
Standard-mode is the default selected mode at power-up or after reset.
Table 17.
I2CSCLL - Clock Rate Low register (indirect address 02h) bit allocation
6
5
4
L6
L5
L4
7
L7
3
L3
2
L2
1
L1
0
L0
Table 18.
Bit
7:0
I2CSCLL - Clock Rate Low register (indirect address 02h) bit description
Symbol
Description
L[7:0]
Eight bits defining the LOW state of SCL.
Table 19.
I2CSCLH - Clock Rate High register (indirect address 03h) bit allocation
6
5
4
H6
H5
H4
7
3
2
1
0
H7
H3
H2
H1
H0
Table 20.
Bit
7:0
I2CSCLH - Clock Rate High register (indirect address 03h) bit description
Symbol
Description
H[7:0]
Eight bits defining the HIGH state of SCL.
f
SCL
I2CSCLH
T
osc
I2CSCLL
+
t
r
t
f
+
+
----------------------------------------------------------------------------------------------
=
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