參數(shù)資料
型號(hào)： PCA9665N
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Fm+ parallel bus to I2C-bus controller
中文描述： I2C BUS CONTROLLER, PDIP20
封裝： 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20
文件頁(yè)數(shù)： 88/91頁(yè)
文件大?。?/td> 372K
代理商： PCA9665N
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
88 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Modifications:
(continued)
Table 49
, sub-section “Bus timing”:
–
changed Min value for t
h(A)
from 7 ns to 13 ns
–
changed Min value for t
w(RDL)
from 7 ns to 20 ns
–
changed Min value for t
w(WRL)
from 7 ns to 20 ns
–
changed Min value for t
su(Q)
from 7 ns to 12 ns
–
changed Min value for t
w(RDH)
from 12 ns to 18 ns
–
changed Min value for t
w(WRH)
from 12 ns to 18 ns
Table 50 “Dynamic characteristics (2.5 volt)
[1][2][3]
”
:
–
added sub-sections “Initialization timing” and “Serial interface initialization timing”
–
sub-section “INT timing”: changed t
as(int)
from (Typ) “<tbd>” to (Max) “550 ns”
–
sub-section “INT timing”: changed t
das(int)
from (Typ) “<tbd>” to (Max) “20 ns”
Table 50
, sub-section “Bus timing”:
–
changed Min value for t
h(A)
from 9 ns to 13 ns
–
changed Min value for t
w(RDL)
from 9 ns to 20 ns
–
changed Min value for t
w(WRL)
from 9 ns to 20 ns
–
changed Min value for t
su(Q)
from 8 ns to 12 ns
–
changed Min value for t
w(RDH)
from 12 ns to 18 ns
–
changed Min value for t
w(WRH)
from 12 ns to 18 ns
Figure 36 “Reset timing”
modified
Figure 38 “Bus timing (read cycle)”
modified
Added (new)
Figure 39 “Parallel bus timing (write cycle)”
Table 51 “I
2
C-bus frequency and timing specifications”
:
–
t
VD;ACK
(Min) changed: (Standard-mode) from 0.3
μ
s to 0.05
μ
s; (Fast-mode) from 0.1
μ
s to
0.05
μ
s
–
t
VD;DAT
(Min) changed: (Fast-mode Plus) from “<tbd>” to “50 ns”
–
t
SP
(Max) changed: (Fast-mode Plus) from “<tbd>” to “50 ns”
Added (new)
Figure 42 “I
2
C-bus timing diagram”
Figure 43 “Test circuitry for switching times”
modified (at switch, “6.0 V” changed to “V
DD
×
2”
Table 52
: modified test t
d(DV)
changed S1 value from “6 V” to “V
DD
×
2”
Added (new)
Figure 44 “Test circuitry for open-drain switching times”
and
Table 53
.
20060807
Objective data sheet
PCA9665_1
-
-
Table 58.
Document ID
Revision history
…continued
Release date
Data sheet status
Change notice
Supersedes
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