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| 型號： | PCA9665N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Fm+ parallel bus to I2C-bus controller |
| 中文描述： | I2C BUS CONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, SOT146-1, DIP-20 |
| 文件頁數(shù)： | 76/91頁 |
| 文件大小： | 372K |
| 代理商： | PCA9665N |
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PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
76 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
[1]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2]
t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
C
b
= total capacitance of one bus line in pF.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCLs falling edge.
[3]
[4]
[5]
[6]
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[7]
Table 51.
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
= 2.5 V
±
0.2 V and
3.3 V
±
0.3 V; T
amb
=
40
°
C to +85
°
C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
.
Symbol
Parameter
Conditions
Standard-mode
I
2
C-bus frequency and timing specifications
I
2
C-bus
Min
0
4.7
Fast-mode I
2
C-bus
Fast-mode Plus
I
2
C-bus
Min
0
0.5
Unit
Max
100
-
Min
0
1.3
Max
400
-
Max
1000
-
f
SCL
t
BUF
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition
set-up time for a
repeated START
condition
set-up time for STOP
condition
data hold time
data valid acknowledge
time
data valid time
data set-up time
LOW period of the SCL
clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by
the input filter
[1]
kHz
μ
s
t
HD;STA
4.0
-
0.6
-
0.26
-
μ
s
t
SU;STA
4.7
-
0.6
-
0.26
-
μ
s
t
SU;STO
4.0
-
0.6
-
0.26
-
μ
s
t
HD;DAT
t
VD;ACK
0
-
0
-
0
-
ns
μ
s
[2]
0.05
3.45
0.05
0.9
0.05
0.45
t
VD;DAT
t
SU;DAT
t
LOW
[3]
50
250
4.7
-
-
-
50
100
1.3
-
-
-
50
50
0.5
-
-
-
ns
ns
μ
s
t
HIGH
4.0
-
0.6
-
0.26
-
μ
s
t
f
[5][6]
-
300
20 + 0.1C
b
[4]
300
-
120
ns
t
r
-
1000
20 + 0.1C
b
[4]
300
-
120
ns
t
SP
[7]
-
50
-
50
-
50
ns
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