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參數資料
| 型號： | NZ48F4L0QTZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數： | 71/106頁 |
| 文件大小： | 1272K |
| 代理商： | NZ48F4L0QTZ |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
71
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
14.1
Memory Partitioning
The L18 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous
read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at
a time can be in program or erase mode.
The flash device supports read-while-write operations with
bus cycle granularity
and not command
granularity. In other words, it is
not
assumed that both bus cycles of a two cycle command (an erase
command for example) will always occur as back to back bus cycles to the flash device. In
practice, code fetches (reads) may be interspersed between write cycles to the flash device, and
they will likely be directed to a different partition than the one being written. This is especially true
when a processor is executing code from one partition that instructs the processor to program or
erase in another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (
Figure 30
, and
Figure 31
). However, a write operation issued between a 2-cycle
commands write sequence causes a command sequence error. (See
Figure 32
)
When reading from the same partition after issuing a Setup command, Status Register data is
returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 30.
Operating Mode with Correct Command Sequence Example
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
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