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參數(shù)資料
| 型號： | NZ48F4L0QTZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 61/106頁 |
| 文件大小： | 1272K |
| 代理商： | NZ48F4L0QTZ |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
61
WA0 must align with the start of an array buffer boundary
1
.
Buffered EFP considerations:
For optimum performance, cycling must be limited below 100 erase cycles per block
2
.
Buffered EFP programs one block at a time; all buffer data must fall within a single block
3
.
Buffered EFP cannot be suspended.
Programming to the flash memory array can occur only when the buffer is full
4
.
Read operation while performing Buffered EFP is not supported.
NOTES:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
2.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay
before checking SR[7] is required to allow the WSM enough time to perform all of its setups and
checks (Block-Lock status, V
PP
level, etc.). If an error is detected, SR[4] is set and Buffered EFP
operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error
occurred due to an incorrect V
PP
level.
Note:
Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to be loaded into the buffer.
11.3.3
Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates
the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the
write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data
programming to the array. For Buffered EFP, the count value for buffer loading is always the
maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential
buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory
array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer
locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an address outside of the
current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any
data previously loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm
will be aborted and the program fail (SR[4]) flag will be set.
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