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參數(shù)資料
| 型號： | NZ48F4L0QTZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 46/106頁 |
| 文件大小： | 1272K |
| 代理商： | NZ48F4L0QTZ |
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Intel StrataFlash Wireless Memory (L18)
April 2005
46
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See
Section 10.0, “Read Operations” on page 50
for details on the available read modes, and see
Section 15.0, “Special Read States” on page 75
for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low power operation following reads during
active mode. After data is read from the memory array and the address lines are quiescent, APS
automatically places the device into standby. In APS, device current is reduced to I
CCAPS
(see
Section 6.1, “DC Current Characteristics” on page 26
).
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted.
During a write operation, address and data are latched on the rising edge of WE# or CE#,
whichever occurs first.
Table 8, “Command Bus Cycles” on page 47
shows the bus cycle sequence
for each of the supported device commands, while
Table 9, “Command Codes and Definitions” on
page 48
describes each command. See
Section 7.0, “AC Characteristics” on page 28
for signal-
timing details.
Note:
Write operations with invalid V
CC
and/or V
PP
voltages can produce spurious results and should not
be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high
-
impedance
(High-Z) state, WAIT is also placed in High-Z.
9.1.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in High-Z, independent of the level
placed on OE#. Standby current, I
CCS
, is the average current measured over any 5 ms time interval,
5
μ
s after CE# is deasserted. During standby, average current is measured over the same time
interval 5
μ
s after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
9.1.5
Reset
As with any automated device, it is important to assert RST# when the system is reset. When the
system comes out of reset, the system processor attempts to read from the flash memory if it is the
system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization
may occur because the flash memory may be providing status information rather than array data.
Flash memory devices from Intel allow proper CPU initialization following a system reset through
the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
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