參數(shù)資料
型號： NS32FX200VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁數(shù)： 48/94頁
文件大?。?/td> 955K
代理商： NS32FX200VF
2.0 Architecture
(Continued)
IDLE1:
Zone
Y
1DSRAM idle control. See IDLEi below.
Zone
Y
2DDRAM wait state control. See WAITi
below.
Zone
Y
2DDRAM idle control. See IDLEi below.
WAIT2:
IDLE2:
WAITi:
Number of T3W (wait) extension cycles (i
e
0, 1,
2)
000 : Seven wait states.
100 : Three wait states.
001 : Six wait states.
101 : Two wait states.
010 : Five wait states.
110 : One wait states.
011 : Four wait states.
111 : Zero wait states.
IDLEi:
(i
e
0,1,2)
0 : No idle cycles after the respective transaction.
1 : Forces two idle cycles after the respective
transaction.
WAIT3:
Zone
Y
3DI/O wait state control.
000 : Sixteen read waits, eighteen write waits.
001 : Fourteen read waits, sixteen write waits.
010 : Twelve read waits, fourteen write waits.
011 : Ten read waits, twelve write waits.
100 : Eight read waits, ten write waits.
101 : Six read waits, eight write waits.
110 : Four read waits, six write waits.
111 : Two read waits, four write waits.
WAITR:
Wait states for DRAM refresh transaction
0 : Three wait states.
1 : Zero wait states.
Upon reset MWAIT is cleared to ‘‘0’’.
2.11.4 Usage Recommendations
Before accessing the DRAM for the first time:
a. Initialize the Refresh Rate Control (RFRT) register in the
TCU.
b. Set Refresh Enabled (RFEN) on.
c. Initialize BMCFG.
d. Initialize MWAIT.
e. Ensure that you provide an appropriate delay time for
components which require a delay between power-up
and the first DRAM access.
2.12 REGISTER SUMMARY
2.12.1 NS32FX100 Registers Access Method
Registers’ address and access are listed in Section 2.12.2.
A byte transaction must be issued to access a byte register.
A word-aligned transaction must be issued to access a dou-
ble-word register.
Unless otherwise specified, all registers are readable and
writable.
Unless otherwise specified, all contents of the registers are
undefined after reset.
Unpredictable results may occur when:
1. Registers are not accessed according to the above rules.
2. Access is made to other locations within the NS32FX100
address space.
Note:
Some instructions, like SBITW and CBITW, issue byte transactions.
Take care not to use these instructions if they are likely to cause
transactions that violate the rules specified in this section. When a
register includes a reserved bit (indicated by ‘‘res’’ field), it must be
written as 0, and its value is undefined when read. Bit 6 of MCFG
(marked as reserved) should be written as ‘‘1’’ where specifically
indicated in this document.
2.12.2 NS32FX200, NS32FV100 and NS32FX100
Registers
MCFG
rw
l
FE0A00
15
6
5
4
3
2
1
0
res
ESDC
EDMA0
ESCAN
EPBMS
ETPHB
ECOUNT
TCU
CSCL
w
l
FE0401
7
5
4
3
0
res
F
res
TIMER
rw
l
FE0402
15
0
TIMER
BUZCFG
rw
l
FE0405
7
6 5
0
BCTRL
res
BUZSWC
w
l
FE0406
15
0
BUZSWC
TSL
r
l
FE0408
7
0
TSL
WDC
rw
l
FE040A
7
0
WDC
MCLON
w
l
FE040C
7
0
MCLON
MCLOFF
w
l
FE040E
7
0
MCLOFF
48
相關(guān)PDF資料
PDF描述
NS32FX210 Facsimile/Data Modem Analog Front End (AFE)
NS32FX210J Facsimile/Data Modem Analog Front End (AFE)
NS32FX210V Facsimile/Data Modem Analog Front End (AFE)
NS32FX211V Microprocessor Compatible Real Time C
NS32FX211 Microprocessor Compatible Real Time C
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX200VF-25 制造商:Texas Instruments 功能描述:
NS32FX210 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX210J 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX210V 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX211 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Microprocessor Compatible Real Time C
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