參數(shù)資料
型號： NS32FX200VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁數(shù)： 47/94頁
文件大?。?/td> 955K
代理商： NS32FX200VF
2.0 Architecture
(Continued)
As in other memory transactions, address bits A12–A15 are
driven onto MA12–MA15 in T1 (non-multiplexed). CAS is
asserted low in T3. Once CAS is asserted, the transaction
may be extended by wait states, denoted by T3W. The
WAIT2 field of the MWAIT register controls the number of
T3W cycles. CAS is asserted low during T3 and T3W. CAS
and RAS0 or RAS1 are de-asserted in T4. During read
transactions WE0 and WE1 are inactive. OE is asserted low
and a word is read from memory. During write transactions
OE is inactive. An even byte is written when WE0 is assert-
ed low. An odd byte is written when WE1 is asserted low. A
word is written when both WE0 and WE1 are asserted low.
On a read transaction OE is asserted low in T2 and de-as-
serted in T4. The write-enable signal(s) is asserted low in T2
and de-asserted in T3 (or last T3W if the transaction is ex-
tended by wait states). A normal DRAM refresh transaction
starts with one idle cycle, denoted T1. During the next cycle,
T2, CAS is asserted low. One cycle later, at T3, RAS0 and
RAS1 are asserted low. The refresh transaction may be ex-
tended by 3
c
T3W cycles, according to the WAITR field of
the MWAIT register. CAS, RAS0 and RAS1 are de-asserted
from T4 through T5.
Some DRAM devices require an initial ‘‘refresh only’’ period,
to charge their voltage pumps, after the power is turned on.
Since these DRAMs should not be accessed during this pe-
riod, it is the software’s responsibility to ensure that the ini-
tialization routine addresses only ROMs until this period has
expired. The DRAM must not be accessed, by software, for
16 slow-clock cycles after reset to ensure clean switching to
the refresh control for the Power Save/Normal mode.
2.11.2.3 Zone 3 (I/O) Transactions
Zone 3 provides extended set-up and hold times. It also
provides more wait states than Zones 0, 1 and 2. The actual
access is extended by four cycles in write and by two cycles
in read. More wait cycles may be programmed, in steps of
two, by the WAIT3 field of the MWAIT register.
A basic transaction starts in T1, when A16–A23, driven by
either the CPU or the NS32FX100, are valid. Then MA1–
MA15, driven by the NS32FX100, are valid in T1. SEL3 is
asserted low by the NS32FX100 in T3.
During a read transaction OE is asserted low on the second
T3W. Once OE is asserted, the transaction may be extend-
ed, according to WAIT3 field of MWAIT register, by wait
states denoted by T3W. OE is de-asserted in T4, SEL3 is
de-asserted two cycles after OE is de-asserted and MA1–
MA15 are driven for one more cycle. The NS32FX100 ex-
tends the transaction beyond T4 of the CPU, HOLD is as-
serted from T2 till T4. A16–A23 are not valid after T4 of the
CPU. If address hold time is required by the memory (or
memory mapped I/O), only MA1–MA15 should be used.
WE0 and WE1 are inactive during read transactions. The
minimum number of waits, for a read transaction, is two.
During a write transaction, an even byte is written when
WE0 is asserted low, an odd byte is written when WE1 is
asserted low and a word is written when both WE0 and WE1
are asserted low. The write enable signal(s) is asserted low
on the second T3W. Once the write enable signal(s) is as-
serted, the transaction may be extended, according to the
WAIT3 field of the MWAIT register, by wait states denoted
by T3W. The write enable signal(s) is de-asserted one cycle
before the last T3W. SEL3 is deasserted in T4. MA1–MA15
are driven for one more cycle. OE is inactive during write
transactions. The minimum number of waits, for a write
transaction, is four.
2.11.2.4 Operation in Freeze Mode
In freeze mode, all output signals except MA1–MA15, CAS,
RAS0, RAS1, SDOUT, SDFDBK, CCLK, FOSCO and SOS-
CO are in TRI-STATE. MA1–MA15 are driven low, and if
less than 0.1 mA is driven, their voltage is below GND
a
0.2V. OE, SEL1, WE0 and WE1 are driven high, and if less
than 0.1 mA is driven, their voltage is above V
CCD
–0.2V.
SEL0 and SEL3 are driven high. When the ETC count
reaches zero in S4 (Freeze and Refresh state) the state
machine reaches S5, refresh transactions are stopped and
CAS, RAS0 and RAS1 are driven low. If refresh is enabled,
these three control signals are driven low during state S5 of
the Power Save mode, and, if less than 0.1 mA is driven,
their voltage is below GND
a
0.2V.
2.11.2.5 On-Chip Registers Access
Access to the on-chip registers is a zero-wait transaction.
2.11.3 Registers
BMCFG: BMC Configuration Register.
7
3
2
1
0
res
DRA0
DPS
DPS:
DRAM page size. Selects the DRAM column size.
00 : Column size
e
256 bytes; RASi controlled by
A17.
For DRAM with 8 muxed address bits; Bank
size
e
128 kbyte.
01 : Column size
e
512 bytes; RASi controlled by
A19.
For DRAM with 9 muxed address bits; Bank
size
e
512 kbyte.
10 : Column size
e
1024 bytes; RASi controlled
by A21.
For DRAM with 10 muxed address bits; Bank
size
e
2 Mbyte.
11 : Column size
e
2048 bytes; only RAS0Dno
RAS1.
For DRAM with 11 muxed address bits; one
bank of 8 Mbyte.
DRA0:
DRAM At 0DControls the assignment of low
4 Mbyte addresses.
0 : Zone
Y
0DROM
1 : Zone
Y
2DDRAM
When DPS
e
11 and DRA0
e
0, the lower half of the
DRAM bank is not accessible. Upon reset the implemented
bits are cleared to ‘‘0’’.
MWAIT: Memory Wait State Register.
15
14
12
11
10
8
7
6
4
3
2
0
WAITR
WAIT3
IDLE2
WAIT2
IDLE1
WAIT1
IDLE0
WAIT0
WAIT0:
Zone
Y
0DROM wait state control. See WAITi be-
low.
Zone
Y
0DROM idle control. See IDLEi below.
Zone
Y
1DSRAM wait state control. See WAITi
below.
IDLE0:
WAIT1:
47
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