參數(shù)資料
型號: NS32FX200VF
廠商: National Semiconductor Corporation
英文描述: System Controller
中文描述: 系統(tǒng)控制器
文件頁數(shù): 39/94頁
文件大?。?/td> 955K
代理商: NS32FX200VF
2.0 Architecture
(Continued)
Accessing MWSIO while the MWIRE is busy
(MWCSR.BUSY
e
1) may cause unpredictable
results.
MWCSR: MICROWIRE Control and Status register.
7
5
4
3
1
0
res
CLKM
CDV
BUSY
BUSY:
Read only. Set to ‘‘1’’ during MWIRE transaction.
Cleared to ‘‘0’’ on termination. Used also as the
MICROWIRE interrupt source.
CDV:
Clock Divider.
Divides the MCLK clock by 2
**
n, where n
e
[
0..5
]
, to generate the MWIRE shift clock.
000 : Non divided MCLK
001 : MCLK/2
010 : MCLK/4
011 : MCLK/8
100 : MCLK/16
101 : MCLK/32
Other : Reserved
CLKM:
Clocking mode:
0 : MWSO changed on MWSK rising edge.
MWSK clock is high when MWIRE is idle.
1 : MWSO changed on MWSK falling edge.
MWSK clock is low when MWIRE is idle.
TL/EE/11331–26
FIGURE 2-21. MICROWIRE Transaction (CLKM
e
0)
TL/EE/11331–27
FIGURE 2-22. MICROWIRE Transaction (CLKM
e
1)
39
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