參數(shù)資料
型號: NS32FX200VF
廠商: National Semiconductor Corporation
英文描述: System Controller
中文描述: 系統(tǒng)控制器
文件頁數(shù): 21/94頁
文件大?。?/td> 955K
代理商: NS32FX200VF
2.0 Architecture
(Continued)
SLS Pulse Generation
Scan Line Sync (SLS) is generated by a timer according to a
calculated delay (in CTTL cycles) from the beginning of the
SPP pulse. The delay between the beginning of SPP and
the leading edge of SLS, SLS pulse width, and SLS polarity
are software programmable.
The first pixel clock after SPP may be distorted. SLS must
be programmed so that this pixel is ignored.
Active Video Window and Peak Detector Window
Generation
The active Video Window, signaling the valid data window,
and the Peak Detector Window, signaling the programmable
window for Automatic Background Control, are generated
by timers which are triggered by SPP and clocked by
SPCLK.
Scanner Interrupt Generation
The scanner interrupt is a rising-edge interrupt, generated at
the beginning of a time slot which is defined by the Scanner
Interrupt Time-Slot register (SITSL).
2.4.2.3 Video Handling Block
The Video Handling Block is an Analog-to-Digital convertor
for the analog video signal. It enables shading, half-toning
and bi-level support with Automatic Background Control
(ABC). It also allows pixel generation control, using external
circuitry.
TL/EE/11331–13
Note 1:
The delay is controlled by the respective register (SLSD, SAVWD or SPDWD).
Note 2:
Measured in CTTL cycles.
Note 3:
Measured in SPCLK cycles.
FIGURE 2-8. Scanner Period Control Signals
TL/EE/11331–14
FIGURE 2-9. Block Diagram of Scanner’s Video Handling Block
21
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