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參數(shù)資料
| 型號： | NS32FX200VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 29/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX200VF |
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2.0 Architecture
(Continued)
b. Initialize the PRNTC module to work with an external
clock.
c. Initialize DMA channel 1 registers without enabling the
channel (set CNTL1.CHEN
e
0).
d. Set MCFG.ECOUNT, and MCFG.EPBMS to ‘‘1’’ to en-
able the PRNTC module.
e. Set CNTL1.CHEN to ‘‘1’’ to enable DMA channel 1.
f. Issue at least four instructions (may be NOPs).
g. Enable the external clock operation.
2.6 DIRECT MEMORY ACCESS CONTROLLER (DMAC)
2.6.1 Features
#
Four independent channels in NS32FX200, three in
NS32FX100 and NS32FV100
#
Single and double buffering, and auto-initialize modes
#
Fly-By or memory-to-I/O transactions
#
8- or 16-bit wide transactions
#
Maximum throughput 12.5 Mbyte/second
#
Channels configurable as internal or external
2.6.2 Description
The DMA Controller (DMAC) provides independent chan-
nels for transferring blocks of data between memory and
I/O devices with minimal CPU intervention. A block transfer
is composed of several byte or word transfers.
A general DMA channel, with eight registers and a superset
of features, is described first. Any on-chip DMA channel is
either similar to, or a subset of, this general channel. The
four NS32FX200 DMA channels, and the three NS32FX100
and NS32FV100 DMA channels, are described after the de-
scription of the general DMA channel.
2.6.2.1 A General DMA Channel
Memory address, block size and type of operation are set
up prior to DMA activation by programming the appropriate
control registers. Actual byte or word transfers are handled
by the DMA channel in response to I/O device requests.
Upon receiving a transfer request from an I/O device, the
DMA Controller performs the following operations:
1. Acquires control of the bus (via HOLD, HLDA mecha-
nism).
2. Acknowledges the requesting I/O device, or one of sev-
eral requesting I/O devices, according to the priority and
to the values stored in the control registers of the re-
spective channel.
3. Executes the data transfer.
4. Updates the termination status bit (TC bit of the STAT
register) when the specified number of bytes has been
transferred.
2.6.2.2 Transfer Types
Each byte or word transfer can be carried out as one of the
following two types:
Fly-By (Direct) Transfers
In Fly-by mode each data item is transferred using a single
bus cycle without reading the data into the DMA Controller.
This mode offers the fastest transfer rate. Data transfer can-
not occur between two memory elements. One of the ele-
ments must be the I/O device that requested the DMA
transfer. This device is referred to as the implied I/O device.
The other element can be either memory or another I/O
device, and is referred to as the addressed device. The
number of bytes transferred in each cycle is always two. Fly-
by DMA transactions are word aligned; device address and
block length must be even numbers. DMA transfers are con-
trolled by the DMA module registers. A detailed description
of the DMA operation is provided in Section 2.6.3.
Memory-to-I/O (Indirect) Transfers
In Memory-to-I/O mode each data item is transferred using
two bus-cycles. Data transfer cannot occur between two
memory elements. One of the elements must be the I/O
device which requested the DMA transaction. This device is
referred to as the implied I/O device and is 8-bits wide. The
other element can be either memory or another I/O device,
is referred to as the addressed I/O device and is 16-bits
wide. The DMA controller takes care of both byte gathering
and scattering. DMA transfers are controlled by the DMA
module registers. A detailed description of the DMA opera-
tion is provided in Section 2.6.3. Memory-to-I/O transfers
are available only through channel 3.
2.6.2.3 Operation Modes
Each block transfer can be carried out in one of three
modes:
#
Single Buffer
Mode
provides the simplest way to accomplish a
single block transfer operation. It performs
one DMA block transfer, and, when the
transfer is completed, prepares the speci-
fications for the next transfer.
#
Double Buffer
Mode
allows the software to set up the next
block-transfer specification while the cur-
rent block-transfer is in progress.
#
Auto-Initialize
Mode
allows the DMA Controller to continuously
fill the same memory area without soft-
ware intervention.
A detailed description of the various modes of operation is
provided in Section 2.6.3.
2.6.3 Detailed Operation Flow
The DMA operation is controlled through the DMA registers.
The flow of the various DMA operations, using different reg-
isters for each transfer type and operation mode, is detailed
below:
Fly-By Operation
The address for the Fly-by mode is taken from the ADCA
counter register. The DMA channel generates either a read
or a write bus cycle according to the setting of the transfer
direction (DIR) bit in the MODE register. When the DIR bit is
‘‘0’’, a read bus-cycle from the addressed device is per-
formed and the data is written to the implied I/O device.
When the DIR bit is ‘‘1’’, a write bus-cycle to the addressed
cycle is performed, and the data is read from the implied I/O
device. After the two bytes have been transferred, the Block
Length Counter (BLTC) is decremented by two. The Device
Address Counter (ADCA) is incremented or decremented by
two, or remains unchanged, according to the Decrement/In-
crement (DEC) and Device Address Control (ADA) bits in
the MODE register.
29
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