
Table of Contents
(Continued)
2.0 ARCHITECTURE
(Continued)
2.11 Bus and Memory Controller (BMC) ààààààààààààà45
2.11.1 Features ààààààààààààààààààààààààààààà45
2.11.2 Operation àààààààààààààààààààààààààààà45
2.11.2.1 Zones 0, 1 (ROM and SRAM)
Transactions ààààààààààààààààà46
2.11.2.2 Zone 2 (Dynamic Memory)
Transactions (NS32FX200 and
NS32FV100 only) ààààààààààààà46
2.11.2.3 Zone 3 (I/O) Transactions ààààà47
2.11.2.4 Operation in Freeze Modeàààààà47
2.11.2.5 On-Chip Registers Access ààààà47
2.11.3 Registers àààààààààààààààààààààààààààà47
2.11.4 Usage Recommendationsàààààààààààààà48
2.12 Register Summary ààààààààààààààààààààààààààà48
2.12.1 NS32FX100 Registers Access Methodààà48
2.12.2 NS32FX200, NS32FV100 and NS32FX100
Registers àààààààààààààààààààààààààààà48
3.0 SYSTEM INTERFACEààààààààààààààààààààààààààà53
3.1 Power and Grounding ààààààààààààààààààààààààà53
3.2 Clocks and Traps Connectivityàààààààààààààààààà53
3.0 SYSTEM INTERFACE
(Continued)
3.3 Control of Power Consumption ààààààààààààààààà53
3.4 Bus Cyclesààààààààààààààààààààààààààààààààààà54
4.0 DEVICE SPECIFICATIONS àààààààààààààààààààààà62
4.1 NS32FX100 Pin Descriptionsààààààààààààààààààà62
4.1.1 Supplies ààààààààààààààààààààààààààààààà62
4.1.2 Input Signalsàààààààààààààààààààààààààààà62
4.1.3 Output Signals àààààààààààààààààààààààààà63
4.1.4 Input/Output Signalsààààààààààààààààààààà64
4.2 Output Signal Levels àààààààààààààààààààààààààà64
4.2.1 Freeze Mode Output Signalsàààààààààààààà65
4.2.2 Reset/Power Restore Output Signals àààààà65
4.3 Absolute Maximum Ratings àààààààààààààààààààà67
4.4 Electrical Characteristicsààààààààààààààààààààààà67
4.5 Analog Electrical Characteristicsàààààààààààààààà69
4.6 Switching Characteristics àààààààààààààààààààààà70
4.6.1 Definitionsàààààààààààààààààààààààààààààà70
4.6.2 Timing Tablesààààààààààààààààààààààààààà71
4.6.2.1 Output Signals: Internal Propagation
Delays àààààààààààààààààààààààààà71
4.6.2.2 Input Signal Requirementsààààààààà76
APPENDIX A: CODEC TRANSMISSION
PERFORMANCE ààààààààààààààààààààà92
3