參數(shù)資料
型號(hào)： NS32FX200VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 45/94頁(yè)
文件大?。?/td> 955K
代理商： NS32FX200VF
2.0 Architecture
(Continued)
PCEN: Port C Enable.
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
EN0–EN7: Enable bit for Port C output pins.
A pin is driven when its relevant ENi bit is set to
‘‘1’’, or not driven (TRI-STATE) when its relevant
ENi bit is cleared to ‘‘0’’.
The inputs are readable regardless of the state of
the respective ENi bit. Upon reset PCEN is cleared
to ‘‘0’’.
PEXT:
External output port mirror register. 16-bit register.
When this register is read, no external latch pulse
is generated.
When this register is written, an external latch
pulse is generated to enable simultaneous write
into both this register and the external latch.
PMPH: Printer Motor Phase Register. 8-bit register.
The register holds the value to be driven by the
PMPH0–3 pins on the next printer motor interrupt
rising edge. Bits 0–3 control the four phases. Bits
4–7 are reserved.
A double buffer is used to latch the next values and
to drive the pins. The PMPH0–3 pins are always
driving.
Upon reset the pins are driven low.
SMPH: Scanner Motor Phase register. 8-bit register.
The register holds the value to be driven by the
SMPH0–3 pins on the next scanner motor interrupt
rising edge. Bits 0–3 control the four phases. Bits
4–7 are reserved.
A double buffer is used to latch the next values and
to drive the pins. The SMPH0–3 pins are always
driving.
Upon reset the pins are driven low.
2.10.4 Usage Recommendations
When working with the Printer Bitmap Shifter, using DMA
channel 1 to load the shifter, the PBMS.MS5 bit must be
cleared to ‘‘0’’ (PBMS.MS5
e
0).
2.11 BUS AND MEMORY CONTROLLER (BMC)
2.11.1 Features
Y
Direct interface to the CPU bus
Y
Direct interface with ROM, SRAM and I/O devices
Y
Programmable wait-state generator
Y
Supports both 8-bit and 16-bit access requests
interface
with
NS32FV100 only).
Y
Direct
DRAM
(NS32FX200
and
Y
CAS before RAS, DRAM refresh (NS32FX200 and
NS32FV100 only)
2.11.2 Operation
The Bus and Memory Controller (BMC) directly interfaces to
the CPU. It responds to read and write transactions and
generates DMA transactions. The memory controller direct-
ly interfaces to ROM, SRAM and I/O devices. The
NS32FX200 and NS32FV100 also support DRAM devices.
It generates the required memory control and CPU wait sig-
nals.
The BMC decodes the high-order address bits and distin-
guishes between five zones, one zone for access to the
NS32FX100 on-chip memory-mapped registers and four ex-
ternal zones. The wait-state generator inserts a programma-
ble number of wait-states according to the accessed ad-
dress zone.
Address decoding (Hex):
Address: 000000–3FFFFF
(4 Mbyte):
Configurable
Zone
Y
0DROM or
Zone
Y
2DDRAM.
(NS32FX100 always:
Zone
Y
0DROM)
Zone
Y
2DDRAM.
(NS32FX100DReserved)
Zone
Y
0DROM.
Address: 400000–7FFFFF
(4 Mbyte):
Address: 800000–BFFFFF
(4 Mbyte):
Address: C00000–DFFFFF
(2 Mbyte):
Zone
Y
1DSRAM.
Address: E00000–EFFFFF
(1 Mbyte):
Zone
Y
3DI/O.
Address: F00000–FFFFFF
(1 Mbyte):
NS32FX100 registers.
Memory is 16-bit (word)-wide. A system, heavily loaded with
memory and I/O devices, needs address buffers. If re-
quired, additional wait states can be added during access to
the buffered devices by programming the appropriate regis-
ter.
After reset, the first instruction fetch is from address 0, lo-
cated in Zone 0DROM Zone. If a RAM is required in the
lower address space, the boot program should jump to the
upper Zone 0 address space and only then configure the
RAM in the low address space.
In Power Save mode (low running frequency) all memory
transactions are performed as no-wait transactions, regard-
less of the values specified in the Memory Wait State
(MWAIT) register. Memory transactions issued by the CPU
and by the NS32FX100 DMA controller are almost identical.
An NS32FX100 DMA transaction is performed after the
HOLD request issued by the NS32FX100 is acknowledged
by the CPU. Memory signals are driven by the NS32FX100.
They are driven in the same manner for both CPU transac-
tions and NS32FX100 DMA transactions.
1. The CPU drives AD0–AD15 throughout T4 whereas the
NS32FX100 does not drive AD0–AD15 to the end of T4,
thus minimizing potential contention on the AD0–AD15
bus.
2. The NS32FX100 does not drive HBE and address on
AD0–AD15 during T1.
3. The CPU drives ADS in T1 for half a cycle whereas the
NS32FX100 drives ADS from Ti to T1 for one cycle.
The memory device does not need to distinguish between
the two types of transactions, as both are identical for the
memory device. Read transactions are always word-wide.
Write transactions are either byte-wide or word-wide. WE0
controls writing to even bytes and WE1 controls writing to
odd bytes.
45
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