參數(shù)資料
型號(hào)： NS32FX200VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 37/94頁(yè)
文件大?。?/td> 955K
代理商： NS32FX200VF
2.0 Architecture
(Continued)
A transmit interrupt is generated on transmit ready, if not
masked by the UMASK register. A receive interrupt is gener-
ated, if not masked by the UMASK register, on receive
ready for every received character regardless of the occur-
rence of a reception error. A reception error has no effect
on the current or the next data reception. i.e., the current
data is available in the data buffer and the next data recep-
tion will occur in the usual way.
No reception is enabled during break on the UART Receive
(URXD) pin. A high-to-low transition is, therefore, required to
detect a start bit.
The UART data buffers are eight bits wide.
Whenever a new character is received, and the data buffer
is empty, the data buffer and the status register are updat-
ed. Hardware flow control can be implemented either by
software (using the Ports module) or by hardware. When
controlled by hardware, transmission starts only if the
Transmit Enable input pin (UTEN) is asserted low. Once a
byte transmission starts, the UTEN value is ignored till the
stop bit is transmitted.
The Receive Enable output pin (UREN) is inactive (high)
when both the receiver shifter and buffer are full. UREN is
asserted low when the buffer or the shifter is empty.
2.7.3 Registers
URXB:
Reception data buffer. Read only. 8-bit register.
Bit 0 is the first bit serially received.
Bit 7 is cleared during reception of 7-bit charac-
ters.
Reading URXB updates the UCLST.RF status bit.
If a new character is ready in the shifter, the
URXB is updated with the new value after the
current value has been read.
UTXB:
Transmission data buffer. 8-bit register.
Bit 0 is the first bit serially transmitted.
Bit 7 is ignored during transmission of 7-bit char-
acters.
UBRGL:
Low byte of the CTTL clock divider (UBRG). 8-bit
register.
UBRGH: High byte of the CTTL clock divider (UBRG). 8-bit
register.
These two, one-byte, registers are used to gener-
ate a clock, whose frequency is 16 times the
baud rate, according to the following equation:
CTTL/(UBRG
a
1)
e
baud-rate
*
16.
UART Control register.
UCNTL:
Controls the number of data and stop bits, parity
enable/disable and odd/even and break trans-
mission on/off. Upon reset all the non reserved
bits are cleared to ‘‘0’’.
UMASK: UART Mask Interrupts register. Upon reset, the
implemented bits are cleared to ‘‘0’’.
7
2
1
0
res
MTI
MRI
MTI: Mask Transmit Interrupt
0: Transmit Interrupt is not masked
1: Transmit Interrupt is masked
MTI: Mask Receive Interrupt
0: Receive Interrupt is not masked
1: Receive Interrupt is masked
TL/EE/11331–25
FIGURE 2-20. Character Format
37
相關(guān)PDF資料
PDF描述
NS32FX210 Facsimile/Data Modem Analog Front End (AFE)
NS32FX210J Facsimile/Data Modem Analog Front End (AFE)
NS32FX210V Facsimile/Data Modem Analog Front End (AFE)
NS32FX211V Microprocessor Compatible Real Time C
NS32FX211 Microprocessor Compatible Real Time C
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX200VF-25 制造商:Texas Instruments 功能描述:
NS32FX210 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX210J 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX210V 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Facsimile/Data Modem Analog Front End (AFE)
NS32FX211 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Microprocessor Compatible Real Time C
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*