參數(shù)資料
型號(hào): NAND04GA3C2AN6F
廠商: 意法半導(dǎo)體
英文描述: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
中文描述: 4Gbit的,2112字節(jié)的頁,3V供電,多級(jí)NAND閃存
文件頁數(shù): 20/51頁
文件大?。?/td> 374K
代理商: NAND04GA3C2AN6F
6 Device operations
NAND04GA3C2A, NAND04GW3C2A
20/51
Figure 6.
Random Data Output
6.4
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see
Table 8
):
1.
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command).
2.
Five bus cycles are then required to input the Start Address (refer to
Table 6
).
3.
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a page (Column Address = 000h, see
Table
7.
). This allows the data to be output uninterrupted after the latency time (t
BLBH1
), see
Figure 7.
I/O
RB
Address
Inputs
ai08658b
Data Output
Busy
tBLBH1
(Read Busy time)
000h
Cmd
Code
30h
Address
Inputs
Data Output
05h
E0h
5 Add cycles
Col Add 1,2
Main Area
Spare
Area
Row Add 1,2,3
Cmd
Code
Cmd
Code
Cmd
Code
2Add cycles
Col Add 1,2
Main Area
Spare
Area
R
相關(guān)PDF資料
PDF描述
NAND04GW3C2AN6E 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
NAND128R3A2AZA1 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND128W3A0AV6 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND256R3A0AZB6 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND128W4A0CZA6E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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