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參數(shù)資料
| 型號： | MT90871 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 8K Digital Switch (F8KDX) |
| 中文描述： | 靈活的8K的數(shù)字交換機(jī)（F8KDX） |
| 文件頁數(shù)： | 51/65頁 |
| 文件大?。?/td> | 639K |
| 代理商： | MT90871 |
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Data Sheet
MT90871
51
Zarlink Semiconductor Inc.
13.14
Revision Control Register
Address 3FFFh
The revision control register stores the binary value of the silicon revision number. This register is read only.
The
RCR
register is configured as follows:
10
BISTCDB
0
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
9
BISTPDB
0
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
8
BISTSDL
0
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
3
BISTPCB
0
Backplane Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
2
BISTSCL
0
Local Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
1
BISTCCL
0
Local Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
0
BISTPCL
0
Local Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Bit
Name
Reset Value
Description
15-4
Reserved
0
Reserved.
3-0
RC(3:0)
defined by silicon
Revision Control Bits.
Table 47- Revision Control Register (RCR) Bits
Bit
Name
Reset
Description
Table 46- Memory BIST Register (MBISTR) Bits (continued)
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PDF描述 |
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| MT90883 | TDM to Packet Processors |
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90880 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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