參數(shù)資料
型號(hào): MT90871
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: 靈活的8K的數(shù)字交換機(jī)(F8KDX)
文件頁(yè)數(shù): 39/65頁(yè)
文件大小: 639K
代理商: MT90871
Data Sheet
MT90871
39
Zarlink Semiconductor Inc.
13.4
Local Input Channel Delay Registers (LCDR0 to LCDR15)
Address 0003h to 0012h.
Sixteen Local input channel delay registers (LCDR0 to LCDR15) allow users to program the input channel
delay for the Local input data streams LSTi0-15. The possible adjustment is 255 channels and the
LCDR0 to
LCDR15
registers are configured as follows:
:
13.4.1
Local Channel Delay Bits 7-0 (LCD7 - LCD0)
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel
data from the Local stream input pins. The input channel delay can be set to 255 (16Mb/s streams), 127
(8Mb/s streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary.
13.5
Local Input Bit Delay Registers (LIDR0 to LIDR15)
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input
data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s.
LCDRn Bit
(where n = 0 to 15)
Name
Reset
Description
15-8
Reserved
0
Reserved
7-0
LCD(7:0)
0
Local Channel Delay Register
The binary value of these bits refers to the channel delay value for the
Local input stream.
Table 16- Local Channel Delay Register (LCDRn) Bits
Input Stream
Channel Delay
Corresponding
Delay Bits
LCD7-LCD0
0 Channel (Default)
0000 0000
1 Channel
0000 0001
2 Channels
0000 0010
3 Channels
0000 0011
4 Channels
0000 0100
5 Channels
0000 0101
...
...
...
...
253 Channels
1111 1101
254 Channels
1111 1110
255 Channels
1111 1111
Table 17- Local Input Channel Delay Programming Table
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參數(shù)描述
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MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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