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參數(shù)資料
| 型號： | MT90871 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 8K Digital Switch (F8KDX) |
| 中文描述： | 靈活的8K的數(shù)字交換機(jī)（F8KDX） |
| 文件頁數(shù)： | 5/65頁 |
| 文件大?。?/td> | 639K |
| 代理商： | MT90871 |
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Data Sheet
MT90871
5
Zarlink Semiconductor Inc.
FP8i
M10
Frame Pulse Input (5V Tolerant).
This pin accepts the Frame Pulse
signal. The pulse width may be active for 122ns or 244ns at the frame
boundary and the Frame Pulse Width bit (FPW) of the Control Register
must be set Low (default) for a 122ns and set High for a the 244ns pulse
condition.
The device will automatically detect whether an
ST-BUS
or
GCI-BUS
style
frame pulse is applied.
Master Clock Input (5V Tolerant).
This pin accepts a 8.192MHz clock.
The internal Frame Boundary is aligned with the clock falling or rising
edge, as controlled by the C8IPOL bit of the Control Register.
Chip Select (5V Tolerant).
Active low input used by the microprocessor to
enable the microprocessor port access. This input is internally set LOW
during a device RESET.
Data Strobe (5V Tolerant).
This active low input is used in conjunction
with CS to enable the microprocessor port read and write operations.
Read/Write (5V Tolerant).
This input controls the direction of the data bus
lines (D0-D15) during a microprocessor access.
Address 0 - 14 (5V Tolerant).
These pins form the 15-bit address bus to
the internal memories and registers. (Address A0 = LSB).
C8i
P10
CS
A10
DS
C8
R/W
A9
A0 - A14
B1, B4, B5, D5, A3,
A4, C6, B6, A5, A6,
C7, B7, A7, A8, B8
N7, P7, P6, N6, P5,
M6, P4, N5, P3, P2,
N3, N4, M5, N2,
M4, M3
D9
D0 - D15
Data Bus 0 - 15 (5V Tolerant).
These pins form the 16-bit data bus of the
microprocessor port. (Data D0 = LSB).
DTA
Data Transfer Acknowledgment (5V Tolerant).
This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required
to hold a HIGH level. (Max. I
OL
= 10mA).
Test Mode Select (5V Tolerant with internal pull-up).
JTAG signal that
controls the state transitions of the TAP controller.
Test Clock (5V Tolerant).
Provides the clock to the JTAG test logic.
Test Serial Data In (5V Tolerant with internal pull-up).
JTAG serial test
instructions and data are shifted in on this pin.
Test Serial Data Out (5V Tolerant Three-state Output).
JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
Test Reset (5V Tolerant with internal pull-up)
Asynchronously initializes
the JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low
during power-up for JTAG testing. This pin must be held LOW for normal
functional operation of the device.
Device Reset (5V Tolerant with internal pull-up).
This input (active
LOW) asynchronously applies reset and synchronously releases reset to
the device. In the reset state, the outputs LSTo0 - 15 and BSTo0 - 15 are
set to a high or high impedance depending on the state of the LORS and
BORS external control pins, respectively. It clears the device registers and
internal counters. This pin must stay low for more than 2 cycles of input
clock C8i for the reset to be invoked.
TMS
A11
TCK
TDi
B11
B10
TDo
A12
TRST
A14
RESET
C9
Pin Description Table (continued)
Name
Package
Coordinates
Description
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| MT90883 | TDM to Packet Processors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90880 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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