參數(shù)資料
型號(hào)： MT90871
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： 靈活的8K的數(shù)字交換機(jī)（F8KDX）
文件頁數(shù)： 29/65頁
文件大?。?/td> 639K
代理商： MT90871
Data Sheet
MT90871
29
Zarlink Semiconductor Inc.
Figure 16 - Examples of BER transmission channels
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (section 13.13 "Memory BIST Register").
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test.
The memory test result is monitored through the Memory BIST Register when controlled via the
microprocessor interface.
11.0
JTAG Port
The MT90871 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. The JTAG is
intended to be used during the development cycle. The JTAG interface is operational when the MT90871 Core
(V
DD_CORE
) is powered at typical voltage levels.
11.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP
Controller in Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to V
DD_IO
when not
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in a
11.2 "TAP Registers". The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
DD_IO
when not driven from an external source.
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
frame boundary
0
1
2
......
.....
254
3
.....
.....
255
0
1
2
......
.....
254
3
.....
.....
255
0
1
2
......
.....
254
3
.....
.....
255
0
1
Channels containing data (traffic)
Channels containing PRBS sequence
Start Ch=0
Length=256
Start Ch=0
Length=3
Start Ch=254
Length=4
0
0
1
1
FP8i
FP
stream
Once Started BER transmission continues until stopped by the BER control register.
2
2
2
Note: Length = Start Chan. + No. of Consecutive channels
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參數(shù)描述
MT90871AV 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
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MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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