參數(shù)資料
型號(hào)： MT90871
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： 靈活的8K的數(shù)字交換機(jī)（F8KDX）
文件頁數(shù)： 14/65頁
文件大?。?/td> 639K
代理商： MT90871
MT90871
Data Sheet
14
Zarlink Semiconductor Inc.
3.0
Input and Output Offset Programming
3.1
Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local
and Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different
frame boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay
of zero such that Ch0 is the first channel that appears after the frame boundary.
By programming the Backplane or Local input channel delay registers, BCDR0-15 and LCDR0-15, users can
assign the Ch0 position to be located at any one of the channel boundaries in a frame. For delays within
channel boundaries, the input bit delay programming can be used. The use of Input Channel Delay in
combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a resolution
of 1/4 of the bit period.
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (8Mb/s)
3.2
Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with
greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed
on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4
bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 10 and Figure 11 for Input Bit Delay Timing at 16Mb/s and 8Mb/s data rates, respectively.
The Local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR15, corresponding to the Local
data streams, LSTi0 to LSTi15, and the Backplane input delay is defined by the Backplane Input Delay registers,
BIDR0 to BIDR15, which correspond to the Backplane data streams, BSTi0 to BSTi15.
FP8o
C8o
7
2
3
4
5
6
1 0
BSTi0-15/LSTi0-15
Channel Delay = 0
Ch 0
7
2
3
4
5
6
1 0
Ch 1
2
3
1 0
7
2
3
4
5
6
1 0
Ch127
2
3
4
5
6
1 0
Ch126
7 6
7
2
3
4
5
6
1 0
BSTi0-15/LSTi0-15
Channel Delay = 1
Ch127
7
2
3
4
5
6
1 0
Ch 0
2
3
1 0
7
2
3
4
5
6
1 0
Ch126
2
3
4
5
6
1 0
Ch125
7 6
7
2
3
4
5
6
1 0
BSTi0-15/LSTi0-15
Channel Delay = 2
Ch126
7
2
3
4
5
6
1 0
Ch127
2
3
1 0
7
2
3
4
5
6
1 0
Ch125
2
3
4
5
6
1 0
Ch0
7 6
(Default)
Channel Delay,1
Channel Delay, 2
7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90871AV 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90880 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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