參數(shù)資料
型號： MT90871
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： 靈活的8K的數(shù)字交換機（F8KDX）
文件頁數(shù)： 17/65頁
文件大?。?/td> 639K
代理商： MT90871
Data Sheet
MT90871
17
Zarlink Semiconductor Inc.
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16Mb/s
4.0
Port High Impedance Control
4.1
Local Port High Impedance Control
The input pin
LORS
selects whether the Local output streams
LSTo0-15
are set to high impedance at the output
of the MT90871 itself or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the
LCSTo0-1
signals. Setting
LORS
to a LOW state will configure the output streams
LSTo0-15
to transmit bi-state channel data with per-channel
high-impedance determined by external circuits under the control of the
LCSTo0-1
outputs. Setting
LORS
to a
HIGH state will configure the output streams
LSTo0-15
of the MT90871 to invoke a high-impedance output on a
per-channel basis.
The
LORS
pin is an asynchronous input and is expected
to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1
LORS Set LOW
The data (channel control bit) transmitted by
LCSTo0-1
replicates the Local Output Enable Bit (
LE
) of the
Local Connection Memory, with a LOW state indicating that the channel should be set to High Impedance by
external drivers. Refer to section 12.3 "Local Connection Memory Bit Definition".
The
LCSTo0-1
outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the
per-channel high impedance state for specific streams. Eight output streams are allocated to each control line
as follows:
LCSTo0 outputs the channel control bits for streams LSTo0, 2, 4, 6, 8, 10, 12 and 14.
LCSTo1 outputs the channel control bits for streams LSTo1, 3, 5, 7, 9, 11, 13 and 15.
(See also “
Pin Description
”.)
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is
presented in Table 2 "LCSTo Allocation of Channel Control Bits to the Output Streams"
.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2.
1.
The Channel Control Bit corresponding to Stream 0, Channel 0,
LSTo0_Ch0,
is transmitted on
LCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of
C16o
.
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
FP8o
System Clock
131.072 Mhz
BSTo0-1
5/LSTo0-15
Bit Advancement = 0
BSTo0-1
5/LSTo0-15
Bit Advancement = -2
(Default)
Bit Advancement = -6
BSTo0-1
5/LSTo0-15
Bit Advancement = -4
BSTo0-1
5/LSTo0-15
Ch255
Ch255
Ch255
Ch255
Ch0
Ch0
Ch0
Ch0
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 4
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90871AV 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90880 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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