參數(shù)資料
型號: MT90871
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: 靈活的8K的數(shù)字交換機(F8KDX)
文件頁數(shù): 46/65頁
文件大小: 639K
代理商: MT90871
MT90871
Data Sheet
46
Zarlink Semiconductor Inc.
13.9.5
Local Receive BER Length Register (LRXBLR)
Address 00C5h
Local BER Receive Length Register (
LRXBLR
) defines how many channels the BER sequence will be received
during each frame. The
LRXBLR
register is configured as follows:
13.9.6
Local BER Start Receive Register (LBSRR)
Address 00C6h
Local BER Start Receive Register defines the Input Stream and Start Channel and the stream in which the BER
sequence shall be received. The
LBSRR
register is configured as follows:
13.9.7
Local BER Count Register (LBCR)
Address 00C7h
Local BER Count Register contains the number of counted errors. This register is read only. The
LBCR
register is
configured as follows:
Bit
Name
Reset
Description
15-8
Reserved
0
Reserved
.
7-0
LRXBL(7:0)
0
Local Receive BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER receiver. (i.e. Total Channels = Start
Channel + LRXBL value)
Table 30- Local Receive BER Length Register (LRXBLR) Bits
Bit
Name
Reset
Description
15-13
Reserved
0
Reserved.
12-8
LBRSA(4:0)
0
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream to receive
the BER data.
7-0
LBRCA(7:0)
0
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input Start Channel in
which the BER data will be received.
Table 31- Local BER Start Receive Register (LBSRR) Bits
Bit
Name
Reset
Description
15-0
LBC(15:0)
0
Local Bit Error Rate Count
The binary value of the bits define the Local Bit Error count.
Table 32- Local BER Count Register (LBCR) Bits
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參數(shù)描述
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