參數(shù)資料
型號(hào)： MT18HVF6472PY-53EXX
元件分類(lèi)： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： LEAD FREE, DIMM-240
文件頁(yè)數(shù)： 5/47頁(yè)
文件大?。?/td> 1012K
代理商： MT18HVF6472PY-53EXX
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
13
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM
device. This definition includes the selection of a burst length, burst type, CAS latency,
operating mode, DLL reset, write recovery, and power-down mode as shown in Figure 5,
"Mode Register (MR) Definition," on page 14. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify
only a subset of the MR variables, all variables (M0–M14) must be programmed when
the LOAD MODE command is issued.
The mode register is programmed via the LM command (bits BA0–BA1/BA2 all = 0) and
other bits (M0–M13 or M0–M14) will retain the stored information until it is pro-
grammed again or the device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory array, pro-
vided it is performed correctly.
The LOAD MODE command can only be issued (or reissued) when all banks are in the
precharged state. The controller must wait the specified time tMRD before initiating any
subsequent operations such as an ACTIVE command. Violating either of these require-
ments will result in unspecified operation.
Burst Length
Burst length is defined by bits M0–M2 as shown in Figure 5, Mode Register (MR) Defini-
tion. Read and write accesses to the DDR2 SDRAM device are burst-oriented, with the
burst length being programmable to either four or eight. The burst length determines
the maximum number of column locations that can be accessed for a given READ or
WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when the burst length is set to four and by A3–Ai when the
burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3 as shown in Figure 5, "Mode Register (MR) Defini-
tion," on page 14. The ordering of accesses within a burst is determined by the burst
length, the burst type, and the starting column address as shown in Table 6, "Burst Defi-
nition," on page 15. DDR2 SDRAM device support 4-bit burst and 8-bit burst modes
only. For 8-bit burst mode, full interleave address ordering is supported; however,
sequential address ordering is nibble-based.
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