參數(shù)資料
型號(hào): MT18HVF6472PY-53EXX
元件分類(lèi): DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: LEAD FREE, DIMM-240
文件頁(yè)數(shù): 25/47頁(yè)
文件大?。?/td> 1012K
代理商: MT18HVF6472PY-53EXX
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
31
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
AC Timing and Operating Specifications
Table 18:
AC Operating Conditions (Sheet 1 of 4)
Notes: 1–5; notes appear on page 35; 0°C
≤ T
CASE ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-667
-53E
-40E
Units
Notes
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock cycle
time
CL = 5
tCK (5)
3,000
8,000
ps
CL = 4
tCK (4)
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH, tCL)
MIN
(tCH, tCL)
MIN
(tCH, tCL)
ps
Clock jitter
tJIT
TBD
ps
Da
ta
DQ output access time from
CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance
window from CK/CK#
tHZ
tAC
(MAX)
tAC
MAX
tAC
MAX
ps
Data-out low-impedance
window from CK/CK#
tLZ
tAC
(MIN)
tAC
(MAX)
tAC MIN
tAC
MAX
tAC MIN
tAC
MAX
ps
DQ and DM input setup time
relative to DQS
tDS
a
300
350
400
ps
DQ and DM input hold time
relative to DQS
tDH
a
300
350
400
ps
DQ and DM input setup time
relative to DQS
tDS
b
100
150
ps
DQ and DM input hold time
relative to DQS
tDH
b
175
225
275
ps
DQ and DM input pulse width
(for each input)
tDIPW
0.35
tCK
Data hold skew factor
tQHS
340
400
450
ps
DQ–DQS hold, DQS to first
DQ to go nonvalid, per access
tQH
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
ps
Data valid output window
(DVW)
tDVW
tQH -
tDQSQ
tQH -
tDQSQ
tQH -
tDQSQ
ns
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