參數(shù)資料
型號(hào): MT18HVF6472PY-53EXX
元件分類(lèi): DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: LEAD FREE, DIMM-240
文件頁(yè)數(shù): 27/47頁(yè)
文件大?。?/td> 1012K
代理商: MT18HVF6472PY-53EXX
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
33
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
AC Timing and Operating Specifications
Comman
d
and
Addr
ess
Address and control input
pulse width for each input
tIPW
0.6
tCK
Address and control input
setup time
tIS
a
400
500
600
ps
Address and control input
hold time
tIH
a
400
500
600
ps
Address and control input
setup time
tIS
b
200
250
350
ps
Address and control input
hold time
tIH
b
275
375
475
ps
CAS# to CAS# command
delay
tCCD
2
tCK
ACTIVE to ACTIVE (same
bank) command
tRC
55
ns
ACTIVE bank a to ACTIVE
bank b command
tRRD
7.5
ns
ACTIVE to READ or WRITE
delay
tRCD
15
ns
Four Bank Activate period
tFAW
37.5
ns
ACTIVE to PRECHARGE
command
tRAS
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge
command delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write
recovery + precharge time
tDAL
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE to READ
command delay
tWTR
10
7.5
10
ns
PRECHARGE command period
tRP
15
ns
PRECHARGE ALL command
period
tRPA
tRP +
tCK
tRP +
tCK
tRP +
tCK
ns
LOAD MODE command cycle
time
tMRD
2
tCK
CKE low to CK,CK#
uncertainty
tDELAY
tIS + tCK +tIH
ns
Table 18:
AC Operating Conditions (Sheet 3 of 4)
Notes: 1–5; notes appear on page 35; 0°C
≤ T
CASE ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-667
-53E
-40E
Units
Notes
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
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