參數(shù)資料
型號： MT18HVF6472PY-53EXX
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： LEAD FREE, DIMM-240
文件頁數(shù)： 22/47頁
文件大小： 1012K
代理商： MT18HVF6472PY-53EXX
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
29
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
IDD Specifications and Conditions
Table 16:
DDR2 IDD Specifications and Conditions – 1GB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol
-667
-53E
-40E
Units
Operating one device bank active-precharge current; tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD0
1,620
1,440
mA
Operating one device bank active-read-precharge current; IOUT = 0mA; BL =
4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD
= tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1
1,890
1,710
1,620
mA
Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
IDD2P
90
mA
Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
IDD2Q
900
720
630
mA
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD2N
990
810
720
mA
Active power-down current; All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
IDD3P
630
540
450
mA
Slow PDN Exit
MR[12] = 1
180
mA
Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX
(IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3N
1,170
990
810
mA
Operating burst write current; All device banks open, Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD4W
2,790
2,340
1,980
mA
Operating burst read current; All device banks open, Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4R
3,150
2,610
2,070
mA
Burst refresh current; tCK = tCK (IDD); Refresh command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD5
3,780
3,600
3,420
mA
Self refresh current; CK and CK# at 0V; CKE
≤ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING.
IDD6
909090
mA
Operating device bank interleave read current; All device banks interleaving
reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, S# is HIGH
between valid commands; Address bus inputs are STABLE during DESELECTs; Data
bus inputs are SWITCHING; See IDD7 Conditions for detail.
IDD7
5,040
4,680
4,140
mA
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