參數(shù)資料
型號: MT18HVF6472PY-53EXX
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: LEAD FREE, DIMM-240
文件頁數(shù): 20/47頁
文件大?。?/td> 1012K
代理商: MT18HVF6472PY-53EXX
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
27
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
IDD Specifications and Conditions
IDD7 Conditions
2GB, specify detailed timing requirements for IDD7. Changes will be required if timing
parameter changes are made to the specification.
Legend: A = active; RA = read auto precharge; D = deselect. All banks are being inter-
leaved at minimum tRC (IDD) without violating tRRD (IDD) using a BL = 4. Control and
address bus inputs are STABLE during DESELECTs. IOUT = 0mA.
Capacitance
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a con-
siderably more accurate result. JEDEC modules are now designed by using simulations
to close timing budgets.
Table 13:
IDD7 Timing Patterns – 512MB and 1GB
All bank interleave READ operation
Speed Grade
Idd7 Timing Patterns
-40E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-53E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-667
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
Table 14:
IDD7 Timing Patterns – 2GB
All bank interleave READ operation
Speed Grade
Idd7 Timing Patterns
-40E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-53E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-667
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
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