參數(shù)資料
型號(hào): MT18HVF6472PY-53EXX
元件分類(lèi): DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: LEAD FREE, DIMM-240
文件頁(yè)數(shù): 1/47頁(yè)
文件大?。?/td> 1012K
代理商: MT18HVF6472PY-53EXX
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
Features
PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_1.fm - Rev. A 8/05 EN
1
2003 Micron Technology, Inc. All rights reserved.
DDR2 VLP Registered DIMM
MT18HVF6472(P) – 512MB
MT18HVF12872(P) – 1GB
MT18HVF25672(P) – 2GB (Advance)
For component information or data sheets, please refer to the Micron Web site: www.micron.com/products/modules
Features
240-pin, very low profile registered dual in-line
memory module (VLP RDIMM)
Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
Supports ECC error detection and correction
512MB (64 Meg x 72), 1GB (128 Meg x 72)
2GB (256 Meg x 72)
VDD = VDDQ = +1.8V
VDDSPD = +1.7V to +3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, and 5
Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Single rank
Figure 1:
240-Pin VLP DIMM (MO-237)
Notes: 1. Contact Micron for product availability.
2. CL = CAS (READ) Latency; Registered mode
will add one clock cycle to CL.
Options
Marking
Parity
P
Package
240-pin DIMM (lead-free)
Y
Frequency/CAS Latency2
3.0ns @ CL = 5 (DDR2-667)
-667
3.75ns @ CL = 4 (DDR2-533)
-53E
5.0ns @ CL = 3 (DDR2-400)
-40E
PCB Height
Very Low Profile 0.72in. (18.29mm)
Height 0.72in. (18.29mm)
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