參數資料
型號: MSC8103M1200F
廠商: MOTOROLA INC
元件分類: 數字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數: 93/120頁
文件大?。?/td> 1952K
代理商: MSC8103M1200F
2-24
AC Timings
Note:
The timing values refer to minimum system timing requirements. Actual implementation
requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the
specific input and output signals associated with the referenced internal controllers and
supported communication protocols. For example, FCC1 supports ATM/Utopia operation in
slave mode, multi-PHY master direct polling mode, and multi-PHY master multiplexed polling
mode and each of these modes supports its own set of signals; the direction (input or output) of
some of the shared signal names depends on the selected mode.
Figure 2-17. SCC/SMC/SPI/I2C External Clock Diagram
Figure 2-18. TDM Signal Diagram
Figure 2-19. PIO, Timer, and DMA Signal Diagram
Serial input clock
SCC/SMC/SPI/I2C inputs
SCC/SMCSPI/I2C outputs
18b
19b
38b
Serial input clock
TDM inputs
TDM outputs
20
21
40
REFCLK
PIO/TIMER/DMA inputs
PIO/TIMER/DMA outputs
22
23
42
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