參數(shù)資料
型號: MSC8103M1200F
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù): 35/120頁
文件大?。?/td> 1952K
代理商: MSC8103M1200F
1-17
Memory Controller Signals
POE
PSDRAS
PGPL2
Output
Bus Output Enable
Output of the bus GPCM. Controls the output buffer of memory devices during read
operations.
Bus SDRAM RAS
Output from the bus SDRAM controller. This pin should connect to the SDRAM
Row Address Strobe (RAS) input signal.
Bus UPM General-Purpose Line 2
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.
PSDCAS
PGPL3
Output
Bus SDRAM CAS
Output from the bus SDRAM controller. This pin should connect to the SDRAM
Column Address Strobe (CAS) input signal.
Bus UPM General-Purpose Line 3
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.
PGTA
PUPMWAIT
PPBS
PGPL4
Input
Output
GPCM TA
Terminates transactions during GPCM operation. Requires an external pull up
resistor for proper operation.
Bus UPM Wait
Input to the UPM. An external device can hold this pin high to force the UPM to wait
until the device is ready for the operation to continue.
Bus Parity Byte Select
In systems in which data parity is stored in a separate chip, this output is the
byte-select for that chip.
Bus UPM General-Purpose Line 4
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.
PSDAMUX
PGPL5
Output
Bus SDRAM Address Multiplexer
Controls the SDRAM address multiplexer when the MSC8103 is in External Master
mode.
Bus UPM General-Purpose Line 5
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.
Table 1-6. Memory Controller Signals (Continued)
Signal
Data
Flow
Description
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